Message ID | 1426768264-16996-40-git-send-email-John.C.Harrison@Intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 19/03/2015 12:30, John.C.Harrison@Intel.com wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > Udpated the various ring->flush() functions to take a request instead of a ring. Nitpick: "Udpated" -> "Updated". Reviewed-by: Tomas Elf <tomas.elf@intel.com> Thanks, Tomas > Also updated the tracer to include the request id. > > For: VIZ-5115 > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++--- > drivers/gpu/drm/i915/i915_trace.h | 14 +++++++------ > drivers/gpu/drm/i915/intel_ringbuffer.c | 34 +++++++++++++++++++------------ > drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- > 5 files changed, 34 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index 35116d3..2c94c88 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -493,7 +493,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) > * itlb_before_ctx_switch. > */ > if (IS_GEN6(ring->dev)) { > - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); > + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); > if (ret) > return ret; > } > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 96fd8e0..5822429 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -885,7 +885,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, > int ret; > > /* NB: TLBs must be flushed and invalidated before a switch */ > - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > if (ret) > return ret; > > @@ -922,7 +922,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, > int ret; > > /* NB: TLBs must be flushed and invalidated before a switch */ > - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > if (ret) > return ret; > > @@ -940,7 +940,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, > > /* XXX: RCS is the only one to auto invalidate the TLBs? */ > if (ring->id != RCS) { > - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); > if (ret) > return ret; > } > diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h > index f004d3d..f044e29 100644 > --- a/drivers/gpu/drm/i915/i915_trace.h > +++ b/drivers/gpu/drm/i915/i915_trace.h > @@ -377,25 +377,27 @@ TRACE_EVENT(i915_gem_ring_dispatch, > ); > > TRACE_EVENT(i915_gem_ring_flush, > - TP_PROTO(struct intel_engine_cs *ring, u32 invalidate, u32 flush), > - TP_ARGS(ring, invalidate, flush), > + TP_PROTO(struct drm_i915_gem_request *req, u32 invalidate, u32 flush), > + TP_ARGS(req, invalidate, flush), > > TP_STRUCT__entry( > __field(u32, dev) > __field(u32, ring) > + __field(u32, uniq) > __field(u32, invalidate) > __field(u32, flush) > ), > > TP_fast_assign( > - __entry->dev = ring->dev->primary->index; > - __entry->ring = ring->id; > + __entry->dev = req->ring->dev->primary->index; > + __entry->ring = req->ring->id; > + __entry->uniq = req->uniq; > __entry->invalidate = invalidate; > __entry->flush = flush; > ), > > - TP_printk("dev=%u, ring=%x, invalidate=%04x, flush=%04x", > - __entry->dev, __entry->ring, > + TP_printk("dev=%u, ring=%x, request=%u, invalidate=%04x, flush=%04x", > + __entry->dev, __entry->ring, __entry->uniq, > __entry->invalidate, __entry->flush) > ); > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index b7646b7..a29fa40 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -91,10 +91,11 @@ static void __intel_ring_advance(struct intel_engine_cs *ring) > } > > static int > -gen2_render_ring_flush(struct intel_engine_cs *ring, > +gen2_render_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate_domains, > u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > u32 cmd; > int ret; > > @@ -117,10 +118,11 @@ gen2_render_ring_flush(struct intel_engine_cs *ring, > } > > static int > -gen4_render_ring_flush(struct intel_engine_cs *ring, > +gen4_render_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate_domains, > u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > struct drm_device *dev = ring->dev; > u32 cmd; > int ret; > @@ -247,9 +249,10 @@ intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) > } > > static int > -gen6_render_ring_flush(struct intel_engine_cs *ring, > - u32 invalidate_domains, u32 flush_domains) > +gen6_render_ring_flush(struct drm_i915_gem_request *req, > + u32 invalidate_domains, u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > u32 flags = 0; > u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; > int ret; > @@ -318,9 +321,10 @@ gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) > } > > static int > -gen7_render_ring_flush(struct intel_engine_cs *ring, > +gen7_render_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate_domains, u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > u32 flags = 0; > u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; > int ret; > @@ -400,9 +404,10 @@ gen8_emit_pipe_control(struct intel_engine_cs *ring, > } > > static int > -gen8_render_ring_flush(struct intel_engine_cs *ring, > +gen8_render_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate_domains, u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > u32 flags = 0; > u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; > int ret; > @@ -1545,10 +1550,11 @@ i8xx_ring_put_irq(struct intel_engine_cs *ring) > } > > static int > -bsd_ring_flush(struct intel_engine_cs *ring, > +bsd_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate_domains, > u32 flush_domains) > { > + struct intel_engine_cs *ring = req->ring; > int ret; > > ret = intel_ring_begin(ring, 2); > @@ -2351,9 +2357,10 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, > _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); > } > > -static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, > +static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate, u32 flush) > { > + struct intel_engine_cs *ring = req->ring; > uint32_t cmd; > int ret; > > @@ -2463,9 +2470,10 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, > > /* Blitter support (SandyBridge+) */ > > -static int gen6_ring_flush(struct intel_engine_cs *ring, > +static int gen6_ring_flush(struct drm_i915_gem_request *req, > u32 invalidate, u32 flush) > { > + struct intel_engine_cs *ring = req->ring; > struct drm_device *dev = ring->dev; > uint32_t cmd; > int ret; > @@ -2879,11 +2887,11 @@ intel_ring_flush_all_caches(struct drm_i915_gem_request *req) > if (!ring->gpu_caches_dirty) > return 0; > > - ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); > + ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS); > if (ret) > return ret; > > - trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); > + trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); > > ring->gpu_caches_dirty = false; > return 0; > @@ -2900,11 +2908,11 @@ intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) > if (ring->gpu_caches_dirty) > flush_domains = I915_GEM_GPU_DOMAINS; > > - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); > + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); > if (ret) > return ret; > > - trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); > + trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); > > ring->gpu_caches_dirty = false; > return 0; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 2d059d1..55f6f35 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -150,7 +150,7 @@ struct intel_engine_cs { > > void (*write_tail)(struct intel_engine_cs *ring, > u32 value); > - int __must_check (*flush)(struct intel_engine_cs *ring, > + int __must_check (*flush)(struct drm_i915_gem_request *req, > u32 invalidate_domains, > u32 flush_domains); > int (*add_request)(struct intel_engine_cs *ring); >
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 35116d3..2c94c88 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -493,7 +493,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) * itlb_before_ctx_switch. */ if (IS_GEN6(ring->dev)) { - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 96fd8e0..5822429 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -885,7 +885,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, int ret; /* NB: TLBs must be flushed and invalidated before a switch */ - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); if (ret) return ret; @@ -922,7 +922,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, int ret; /* NB: TLBs must be flushed and invalidated before a switch */ - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); if (ret) return ret; @@ -940,7 +940,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, /* XXX: RCS is the only one to auto invalidate the TLBs? */ if (ring->id != RCS) { - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index f004d3d..f044e29 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -377,25 +377,27 @@ TRACE_EVENT(i915_gem_ring_dispatch, ); TRACE_EVENT(i915_gem_ring_flush, - TP_PROTO(struct intel_engine_cs *ring, u32 invalidate, u32 flush), - TP_ARGS(ring, invalidate, flush), + TP_PROTO(struct drm_i915_gem_request *req, u32 invalidate, u32 flush), + TP_ARGS(req, invalidate, flush), TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) + __field(u32, uniq) __field(u32, invalidate) __field(u32, flush) ), TP_fast_assign( - __entry->dev = ring->dev->primary->index; - __entry->ring = ring->id; + __entry->dev = req->ring->dev->primary->index; + __entry->ring = req->ring->id; + __entry->uniq = req->uniq; __entry->invalidate = invalidate; __entry->flush = flush; ), - TP_printk("dev=%u, ring=%x, invalidate=%04x, flush=%04x", - __entry->dev, __entry->ring, + TP_printk("dev=%u, ring=%x, request=%u, invalidate=%04x, flush=%04x", + __entry->dev, __entry->ring, __entry->uniq, __entry->invalidate, __entry->flush) ); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b7646b7..a29fa40 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -91,10 +91,11 @@ static void __intel_ring_advance(struct intel_engine_cs *ring) } static int -gen2_render_ring_flush(struct intel_engine_cs *ring, +gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; u32 cmd; int ret; @@ -117,10 +118,11 @@ gen2_render_ring_flush(struct intel_engine_cs *ring, } static int -gen4_render_ring_flush(struct intel_engine_cs *ring, +gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; struct drm_device *dev = ring->dev; u32 cmd; int ret; @@ -247,9 +249,10 @@ intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) } static int -gen6_render_ring_flush(struct intel_engine_cs *ring, - u32 invalidate_domains, u32 flush_domains) +gen6_render_ring_flush(struct drm_i915_gem_request *req, + u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; u32 flags = 0; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; int ret; @@ -318,9 +321,10 @@ gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) } static int -gen7_render_ring_flush(struct intel_engine_cs *ring, +gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; u32 flags = 0; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; int ret; @@ -400,9 +404,10 @@ gen8_emit_pipe_control(struct intel_engine_cs *ring, } static int -gen8_render_ring_flush(struct intel_engine_cs *ring, +gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; u32 flags = 0; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; int ret; @@ -1545,10 +1550,11 @@ i8xx_ring_put_irq(struct intel_engine_cs *ring) } static int -bsd_ring_flush(struct intel_engine_cs *ring, +bsd_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains) { + struct intel_engine_cs *ring = req->ring; int ret; ret = intel_ring_begin(ring, 2); @@ -2351,9 +2357,10 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); } -static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, +static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 invalidate, u32 flush) { + struct intel_engine_cs *ring = req->ring; uint32_t cmd; int ret; @@ -2463,9 +2470,10 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, /* Blitter support (SandyBridge+) */ -static int gen6_ring_flush(struct intel_engine_cs *ring, +static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 invalidate, u32 flush) { + struct intel_engine_cs *ring = req->ring; struct drm_device *dev = ring->dev; uint32_t cmd; int ret; @@ -2879,11 +2887,11 @@ intel_ring_flush_all_caches(struct drm_i915_gem_request *req) if (!ring->gpu_caches_dirty) return 0; - ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); + ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS); if (ret) return ret; - trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); + trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); ring->gpu_caches_dirty = false; return 0; @@ -2900,11 +2908,11 @@ intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) if (ring->gpu_caches_dirty) flush_domains = I915_GEM_GPU_DOMAINS; - ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); + ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); if (ret) return ret; - trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); + trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); ring->gpu_caches_dirty = false; return 0; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 2d059d1..55f6f35 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -150,7 +150,7 @@ struct intel_engine_cs { void (*write_tail)(struct intel_engine_cs *ring, u32 value); - int __must_check (*flush)(struct intel_engine_cs *ring, + int __must_check (*flush)(struct drm_i915_gem_request *req, u32 invalidate_domains, u32 flush_domains); int (*add_request)(struct intel_engine_cs *ring);