From patchwork Thu Mar 19 12:32:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kahola, Mika" X-Patchwork-Id: 6049261 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CBB259F399 for ; Thu, 19 Mar 2015 12:33:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E33F72052D for ; Thu, 19 Mar 2015 12:33:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CE2A02052C for ; Thu, 19 Mar 2015 12:33:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EAA46EA42; Thu, 19 Mar 2015 05:33:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 200B16EA42 for ; Thu, 19 Mar 2015 05:33:13 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 19 Mar 2015 05:33:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,429,1422950400"; d="scan'208";a="469475126" Received: from sorvi.fi.intel.com ([10.237.72.163]) by FMSMGA003.fm.intel.com with ESMTP; 19 Mar 2015 05:33:08 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Thu, 19 Mar 2015 14:32:35 +0200 Message-Id: <1426768355-14038-1-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425387898-3333-1-git-send-email-mika.kahola@intel.com> References: <1425387898-3333-1-git-send-email-mika.kahola@intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: DP link training optimization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds fast link training support if BDB version is equal or higher than 182 and the feature is supported in VBT. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 4 ++++ drivers/gpu/drm/i915/intel_bios.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 5 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index eb38cd1..f4e413e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1349,6 +1349,7 @@ struct intel_vbt_data { bool edp_support; int edp_bpp; bool edp_low_vswing; + bool edp_flt_enabled; struct edp_power_seq edp_pps; struct { diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c684085..8262195 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -669,6 +669,10 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; dev_priv->vbt.edp_low_vswing = vswing == 0; } + + /* support for fast link training */ + if (bdb->version >= 182) + dev_priv->vbt.edp_flt_enabled = (edp->edp_flt_enabled >> panel_type) & 0x1; } static void diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index 6afd5be..fad7ff7 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -555,6 +555,7 @@ struct bdb_edp { u16 edp_s3d_feature; u16 edp_t3_optimization; u64 edp_vswing_preemph; /* v173 */ + u16 edp_flt_enabled; /* v182 */ } __packed; struct psr_table { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8f7720c..fbe97a9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3472,7 +3472,20 @@ static bool intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) { + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int i; + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); + + /* eDP case */ + if (intel_dp->edp_use_vbt_train_set && dev_priv->vbt.edp_flt_enabled) { + for (i = 0; i < intel_dp->lane_count; i++) + intel_dp->train_set[i] = dev_priv->vbt.edp_vswing | + dev_priv->vbt.edp_preemphasis; + } + intel_dp_set_signal_levels(intel_dp, DP); return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); } @@ -3580,6 +3593,9 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) DP |= DP_PORT_EN; + /* for eDP use link train set from VBT */ + intel_dp->edp_use_vbt_train_set = is_edp(intel_dp); + /* * check if eDP has already trained. Reset voltage swing and * pre-emphasis levels if that's not the case. @@ -3624,6 +3640,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) */ if (intel_dp->link_trained) { DRM_DEBUG_KMS("clock recovery not ok, reset"); + intel_dp->edp_use_vbt_train_set = false; if (!intel_dp_reset_link_train(intel_dp, &DP, DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ba6eda1..fc692e3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -673,6 +673,7 @@ struct intel_dp { int send_bytes, uint32_t aux_clock_divider); bool link_trained; + bool edp_use_vbt_train_set; }; struct intel_digital_port {