| Message ID | 1427201659-22850-1-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 3/24/2015 12:54 PM, Mika Kuoppala wrote: > The faulting virtual address is >32bits and has been moved > to different registers. Add to error state and output upper > register first, in the same line for easy reconstruction of > the fault address. > > v2: correct gen masking (Michel) > v3: s/TBL/TLB (Ville) > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 3 files changed, 15 insertions(+) > Thanks for noticing that last typo... Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6039
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275 273/275
ILK 303/303 303/303
SNB -1 304/304 303/304
IVB 339/339 339/339
BYT 287/287 287/287
HSW 361/361 361/361
BDW 310/310 310/310
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt@gem_userptr_blits@minor-normal-sync PASS(3) DMESG_WARN(1)PASS(1)
PNV igt@gem_userptr_blits@minor-unsync-normal DMESG_WARN(2)PASS(2) DMESG_WARN(1)PASS(1)
*SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip PASS(2) FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'
On Tue, Mar 24, 2015 at 01:01:54PM +0000, Michel Thierry wrote: > On 3/24/2015 12:54 PM, Mika Kuoppala wrote: > >The faulting virtual address is >32bits and has been moved > >to different registers. Add to error state and output upper > >register first, in the same line for easy reconstruction of > >the fault address. > > > >v2: correct gen masking (Michel) > >v3: s/TBL/TLB (Ville) > > > >Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > >--- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++ > > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > > 3 files changed, 15 insertions(+) > > > Thanks for noticing that last typo... > > Reviewed-by: Michel Thierry <michel.thierry@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4dbe743..3ec70a5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -427,6 +427,8 @@ struct drm_i915_error_state { u32 forcewake; u32 error; /* gen6+ */ u32 err_int; /* gen7 */ + u32 fault_data0; /* gen8, gen9 */ + u32 fault_data1; /* gen8, gen9 */ u32 done_reg; u32 gac_eco; u32 gam_ecochk; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 2f7cbd3..1d4e60d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -386,6 +386,11 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, if (INTEL_INFO(dev)->gen >= 6) { err_printf(m, "ERROR: 0x%08x\n", error->error); + + if (INTEL_INFO(dev)->gen >= 8) + err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", + error->fault_data1, error->fault_data0); + err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); } @@ -1171,6 +1176,11 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (IS_GEN7(dev)) error->err_int = I915_READ(GEN7_ERR_INT); + if (INTEL_INFO(dev)->gen >= 8) { + error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); + error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); + } + if (IS_GEN6(dev)) { error->forcewake = I915_READ(FORCEWAKE); error->gab_ctl = I915_READ(GAB_CTL); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b84ee6..b522eb6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1306,6 +1306,9 @@ enum skl_disp_power_wells { #define ERR_INT_FIFO_UNDERRUN_A (1<<0) #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) +#define GEN8_FAULT_TLB_DATA0 0x04b10 +#define GEN8_FAULT_TLB_DATA1 0x04b14 + #define FPGA_DBG 0x42300 #define FPGA_DBG_RM_NOCLAIM (1<<31)
The faulting virtual address is >32bits and has been moved to different registers. Add to error state and output upper register first, in the same line for easy reconstruction of the fault address. v2: correct gen masking (Michel) v3: s/TBL/TLB (Ville) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 3 files changed, 15 insertions(+)