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[5/5] drm/i915: Enable mmeory self-refresh on 85x

Message ID 1427787445-20244-6-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä March 31, 2015, 7:37 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We currently lack the code to enable CxSR on 85x. The hardware seems to
have a few different SR modes, but let's ust use the most
straightforward one and hope this saves a bit of extra power.

I haven't observed any ill effects with this enabled on my 855.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

Comments

Shuang He March 31, 2015, 11:14 a.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6096
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                                  338/338              338/338
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  309/309              309/309
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..45308c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1498,6 +1498,7 @@  enum skl_disp_power_wells {
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
 
 #define MI_STATE	0x020e4 /* gen2 only */
+#define   MI_SR_EN				(3 << 3) /* 85x only */
 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fa4ccb3..d23fb82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -327,6 +327,10 @@  void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 		I915_WRITE(INSTPM, val);
+	} else if (IS_I85X(dev)) {
+		val = enable ? _MASKED_BIT_ENABLE(MI_SR_EN) :
+			       _MASKED_BIT_DISABLE(MI_SR_EN);
+		I915_WRITE(MI_STATE, val);
 	} else {
 		return;
 	}