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[18/19] drm/i915: Limit CHV max cdclk

Message ID 1427800461-5350-1-git-send-email-mika.kahola@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Kahola, Mika March 31, 2015, 11:14 a.m. UTC 
Limit CHV maximum cdclk to 320MHz.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 736df3e..5ed40df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5037,7 +5037,7 @@  static void intel_update_max_cdclk(struct drm_device *dev)
 		else
 			dev_priv->max_cdclk_freq = 540000;
 	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->max_cdclk_freq = 400000;
+		dev_priv->max_cdclk_freq = IS_CHERRYVIEW(dev) ? 320000 : 400000;
 	} else {
 		/* otherwise assume cdclk is fixed */
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;