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[1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info

Message ID 1427821163-25522-2-git-send-email-jeff.mcgee@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

jeff.mcgee@intel.com March 31, 2015, 4:59 p.m. UTC
From: Jeff McGee <jeff.mcgee@intel.com>

BXT uses a subset of the SKL fuse registers, because it has at
most 1 slice and at most 6 EU per subslice.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ec661fe..81afd31 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -733,6 +733,53 @@  static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
 		info->has_subslice_pg = 0;
 		info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
+	} else if (IS_BROXTON(dev)) {
+		const int ss_max = 4;
+		int ss;
+		u32 fuse2, eu_disable, ss_disable;
+
+		fuse2 = I915_READ(GEN8_FUSE2);
+		ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
+			     GEN9_F2_SS_DIS_SHIFT;
+		eu_disable = I915_READ(GEN8_EU_DISABLE0);
+
+		info->slice_total = 1;
+		info->subslice_per_slice = ss_max - hweight32(ss_disable);
+		info->subslice_total = info->subslice_per_slice;
+
+		/*
+		 * Iterate through enabled subslices to count the total
+		 * enabled EU.
+		*/
+		for (ss = 0; ss < ss_max; ss++) {
+			if (ss_disable & (0x1 << ss))
+				/* skip disabled subslice */
+				continue;
+
+			/*
+			 * BXT can have at most 6 EU per subslice. So only the
+			 * lowest 6 bits of the 8-bit EU disable field are
+			 * valid.
+			*/
+			info->eu_total += 6 - hweight8((eu_disable >>
+							(ss * 8)) & 0x3f);
+		}
+
+		/*
+		 * BXT expected to always have a uniform distribution of EU
+		 * across subslices.
+		*/
+		info->eu_per_subslice = info->subslice_total ?
+					info->eu_total / info->subslice_total :
+					0;
+		/*
+		 * BXT supports subslice power gating on devices with more than
+		 * one subslice, and supports EU power gating on devices with
+		 * more than one EU pair per subslice.
+		*/
+		info->has_slice_pg = 0;
+		info->has_subslice_pg = (info->subslice_total > 1);
+		info->has_eu_pg = (info->eu_per_subslice > 2);
 	}
 	DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 	DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);