From patchwork Tue Mar 31 16:59:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 6132561 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A9731BF4A6 for ; Tue, 31 Mar 2015 16:59:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DADD320142 for ; Tue, 31 Mar 2015 16:59:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DC8F82015A for ; Tue, 31 Mar 2015 16:59:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 642356E736; Tue, 31 Mar 2015 09:59:09 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id A7EDB6E733 for ; Tue, 31 Mar 2015 09:59:06 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 31 Mar 2015 09:59:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,502,1422950400"; d="scan'208";a="549031535" Received: from jeffdesk.fm.intel.com ([10.19.123.159]) by orsmga003.jf.intel.com with ESMTP; 31 Mar 2015 09:59:06 -0700 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2015 09:59:22 -0700 Message-Id: <1427821163-25522-2-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.3.3 In-Reply-To: <1427821163-25522-1-git-send-email-jeff.mcgee@intel.com> References: <1427821163-25522-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee BXT uses a subset of the SKL fuse registers, because it has at most 1 slice and at most 6 EU per subslice. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index ec661fe..81afd31 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -733,6 +733,53 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; info->has_subslice_pg = 0; info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; + } else if (IS_BROXTON(dev)) { + const int ss_max = 4; + int ss; + u32 fuse2, eu_disable, ss_disable; + + fuse2 = I915_READ(GEN8_FUSE2); + ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> + GEN9_F2_SS_DIS_SHIFT; + eu_disable = I915_READ(GEN8_EU_DISABLE0); + + info->slice_total = 1; + info->subslice_per_slice = ss_max - hweight32(ss_disable); + info->subslice_total = info->subslice_per_slice; + + /* + * Iterate through enabled subslices to count the total + * enabled EU. + */ + for (ss = 0; ss < ss_max; ss++) { + if (ss_disable & (0x1 << ss)) + /* skip disabled subslice */ + continue; + + /* + * BXT can have at most 6 EU per subslice. So only the + * lowest 6 bits of the 8-bit EU disable field are + * valid. + */ + info->eu_total += 6 - hweight8((eu_disable >> + (ss * 8)) & 0x3f); + } + + /* + * BXT expected to always have a uniform distribution of EU + * across subslices. + */ + info->eu_per_subslice = info->subslice_total ? + info->eu_total / info->subslice_total : + 0; + /* + * BXT supports subslice power gating on devices with more than + * one subslice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + info->has_slice_pg = 0; + info->has_subslice_pg = (info->subslice_total > 1); + info->has_eu_pg = (info->eu_per_subslice > 2); } DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);