From patchwork Tue Mar 31 16:59:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 6132571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5B47D9F349 for ; Tue, 31 Mar 2015 16:59:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 893D62015A for ; Tue, 31 Mar 2015 16:59:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A2B0820142 for ; Tue, 31 Mar 2015 16:59:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2522A6E737; Tue, 31 Mar 2015 09:59:12 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F49E6E737 for ; Tue, 31 Mar 2015 09:59:11 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 31 Mar 2015 09:59:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,502,1422950400"; d="scan'208";a="549031554" Received: from jeffdesk.fm.intel.com ([10.19.123.159]) by orsmga003.jf.intel.com with ESMTP; 31 Mar 2015 09:59:11 -0700 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Mar 2015 09:59:23 -0700 Message-Id: <1427821163-25522-3-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.3.3 In-Reply-To: <1427821163-25522-1-git-send-email-jeff.mcgee@intel.com> References: <1427821163-25522-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee BXT uses the same power gate control ack message registers as SKL. BXT makes use of additional fields which indicate the power gating state of each subslice in BXT's single slice. Signed-off-by: Jeff McGee Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_debugfs.c | 35 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 007c7d7..6c5ba28 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4566,6 +4566,41 @@ static int i915_sseu_status(struct seq_file *m, void *unused) eu_per = max(eu_per, eu_cnt); } } + } else if (IS_BROXTON(dev)) { + const int ss_max = 3; + int ss; + u32 s_reg, eu_reg[2], eu_mask[2]; + + s_reg = I915_READ(GEN9_SLICE0_PGCTL_ACK); + eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); + eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | + GEN9_PGCTL_SSA_EU19_ACK | + GEN9_PGCTL_SSA_EU210_ACK | + GEN9_PGCTL_SSA_EU311_ACK; + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | + GEN9_PGCTL_SSB_EU19_ACK | + GEN9_PGCTL_SSB_EU210_ACK | + GEN9_PGCTL_SSB_EU311_ACK; + + if (s_reg & GEN9_PGCTL_SLICE_ACK) { + + s_tot = 1; + for (ss = 0; ss < ss_max; ss++) { + unsigned int eu_cnt; + + if (!(s_reg & (GEN9_PGCTL_SS0_ACK << (2 * ss)))) + /* skip disabled subslice */ + continue; + + ss_per++; + eu_cnt = 2 * hweight32(eu_reg[ss/2] & + eu_mask[ss%2]); + eu_tot += eu_cnt; + eu_per = max(eu_per, eu_cnt); + } + } + ss_tot = ss_per; } seq_printf(m, " Enabled Slice Total: %u\n", s_tot); seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7e1a0fd9..be6554f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6275,6 +6275,9 @@ enum skl_disp_power_wells { #define GEN9_SLICE1_PGCTL_ACK 0x8050 #define GEN9_SLICE2_PGCTL_ACK 0x8054 #define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS0_ACK (1 << 2) /* Only for SLICE0 */ +#define GEN9_PGCTL_SS1_ACK (1 << 4) /* Only for SLICE0 */ +#define GEN9_PGCTL_SS2_ACK (1 << 6) /* Only for SLICE0 */ #define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c #define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060