From patchwork Thu Apr 9 14:34:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 6187951 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B362FBF4A7 for ; Thu, 9 Apr 2015 14:34:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C2B142035B for ; Thu, 9 Apr 2015 14:34:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BCA7420375 for ; Thu, 9 Apr 2015 14:34:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57CBF720F3; Thu, 9 Apr 2015 07:34:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F3E26E7C7; Thu, 9 Apr 2015 07:34:13 -0700 (PDT) Received: by wiun10 with SMTP id n10so100571771wiu.1; Thu, 09 Apr 2015 07:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hfn4prWs0MofTvDG34/8F+9LswTvj5UodvzdRXf1+fs=; b=DdxnhcET7ipcAMqW9+DPA4WTFG7LZ/H/TXXQMfW1Hlm90LURe/ycg6PN7/Rv8L4R07 8fpwAtNfTTu3Pea70fS3VXaaBR9ThDcB3+eAjtpI27QJH4kNHL8k0vn2CdL/ukssbf+g 8zLAy5h4EutBxEPrQoylcyVVvr8HYqdImgaYyOoyNI+wu0YRyuZD2l7d58pgsHu7Oc9J JR9OL15JehtUqFN/NAz+aMx/VDoFhdOL4pLCgRBhCOZchk/xMYsFLpEBBuv37qfwp+pj dXjijEJ30guCq3G8gmP/8GzudgCRSwKgmbDr2Vx7L9BFjy/4VjrXN5NorYMDykCIWd3F 8OTg== X-Received: by 10.194.122.196 with SMTP id lu4mr61104190wjb.154.1428590052839; Thu, 09 Apr 2015 07:34:12 -0700 (PDT) Received: from localhost (port-21116.pppoe.wtnet.de. [46.59.144.37]) by mx.google.com with ESMTPSA id lx10sm20381057wjb.17.2015.04.09.07.34.11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Apr 2015 07:34:12 -0700 (PDT) From: Thierry Reding To: dri-devel@lists.freedesktop.org Date: Thu, 9 Apr 2015 16:34:05 +0200 Message-Id: <1428590049-20357-2-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.3.2 In-Reply-To: <1428590049-20357-1-git-send-email-thierry.reding@gmail.com> References: <1428590049-20357-1-git-send-email-thierry.reding@gmail.com> Cc: Arnd Bergmann , David Airlie , Catalin Marinas , intel-gfx@lists.freedesktop.org, Will Deacon , Russell King , linux-arm-kernel@lists.infradead.org Subject: [Intel-gfx] [PATCH 2/6] drm/cache: Implement drm_clflush_*() for ARM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Add implementations for drm_clflush_*() on ARM by borrowing code from the DMA mapping API implementation. Unfortunately ARM doesn't export an API to flush caches on a page by page basis, so this replicates most of the code. Reviewed-by: Rob Clark Tested-by: Rob Clark Signed-off-by: Thierry Reding --- drivers/gpu/drm/drm_cache.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 9a62d7a53553..200d86c3d72d 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -67,6 +67,41 @@ static void drm_cache_flush_clflush(struct page *pages[], } #endif +#if defined(CONFIG_ARM) + +#include +#include +#include +#include + +static void drm_clflush_page(struct page *page) +{ + enum dma_data_direction dir = DMA_TO_DEVICE; + phys_addr_t phys = page_to_phys(page); + size_t size = PAGE_SIZE; + void *virt; + + if (PageHighMem(page)) { + if (cache_is_vipt_nonaliasing()) { + virt = kmap_atomic(page); + dmac_map_area(virt, size, dir); + kunmap_atomic(virt); + } else { + virt = kmap_high_get(page); + if (virt) { + dmac_map_area(virt, size, dir); + kunmap_high(page); + } + } + } else { + virt = page_address(page); + dmac_map_area(virt, size, dir); + } + + outer_flush_range(phys, phys + PAGE_SIZE); +} +#endif + void drm_clflush_pages(struct page *pages[], unsigned long num_pages) { @@ -94,6 +129,11 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) (unsigned long)page_virtual + PAGE_SIZE); kunmap_atomic(page_virtual); } +#elif defined(CONFIG_ARM) + unsigned long i; + + for (i = 0; i < num_pages; i++) + drm_clflush_page(pages[i]); #else printk(KERN_ERR "Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1); @@ -118,6 +158,11 @@ drm_clflush_sg(struct sg_table *st) if (wbinvd_on_all_cpus()) printk(KERN_ERR "Timed out waiting for cache flush.\n"); +#elif defined(CONFIG_ARM) + struct sg_page_iter sg_iter; + + for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) + drm_clflush_page(sg_page_iter_page(&sg_iter)); #else printk(KERN_ERR "Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1);