| Message ID | 1428612126-4634-1-git-send-email-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Apr 09, 2015 at 01:42:06PM -0700, clinton.a.taylor@intel.com wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > Latest version of the "CHV DPIO programming notes" no longer requires writes > to TX DW 11 to fix a +2UI interpair skew issue. The current code from > April 2014 was actually causing additional skew issues between all > TMDS pairs. > > ver2: added same treatment to intel_dp.c based on Ville's testing. > > Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Yep this fixes the DP link training issues on both of the problematic displays I have (HP ZR24w and ASUS PB278Q). Nice work. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 5 ----- > drivers/gpu/drm/i915/intel_hdmi.c | 5 ----- > 2 files changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 1b87969..f106763 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2740,11 +2740,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) > > /* Program Tx lane latency optimal setting*/ > for (i = 0; i < 4; i++) { > - /* Set the latency optimal bit */ > - data = (i == 1) ? 0x0 : 0x6; > - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), > - data << DPIO_FRC_LATENCY_SHFIT); > - > /* Set the upar bit */ > data = (i == 1) ? 0x0 : 0x1; > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 26222e6..3cef326 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) > > /* Program Tx latency optimal setting */ > for (i = 0; i < 4; i++) { > - /* Set the latency optimal bit */ > - data = (i == 1) ? 0x0 : 0x6; > - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), > - data << DPIO_FRC_LATENCY_SHFIT); > - > /* Set the upar bit */ > data = (i == 1) ? 0x0 : 0x1; > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), > -- > 1.7.9.5
On Fri, 10 Apr 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Thu, Apr 09, 2015 at 01:42:06PM -0700, clinton.a.taylor@intel.com wrote: >> From: Clint Taylor <clinton.a.taylor@intel.com> >> >> Latest version of the "CHV DPIO programming notes" no longer requires writes >> to TX DW 11 to fix a +2UI interpair skew issue. The current code from >> April 2014 was actually causing additional skew issues between all >> TMDS pairs. >> >> ver2: added same treatment to intel_dp.c based on Ville's testing. >> >> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > > Yep this fixes the DP link training issues on both of the problematic > displays I have (HP ZR24w and ASUS PB278Q). Nice work. > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pushed to drm-intel-next-fixes (because chv support is no longer flagged preliminary since drm-next and v4.1). Thanks for the patch and review. BR, Jani. > >> --- >> drivers/gpu/drm/i915/intel_dp.c | 5 ----- >> drivers/gpu/drm/i915/intel_hdmi.c | 5 ----- >> 2 files changed, 10 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 1b87969..f106763 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -2740,11 +2740,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) >> >> /* Program Tx lane latency optimal setting*/ >> for (i = 0; i < 4; i++) { >> - /* Set the latency optimal bit */ >> - data = (i == 1) ? 0x0 : 0x6; >> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), >> - data << DPIO_FRC_LATENCY_SHFIT); >> - >> /* Set the upar bit */ >> data = (i == 1) ? 0x0 : 0x1; >> vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c >> index 26222e6..3cef326 100644 >> --- a/drivers/gpu/drm/i915/intel_hdmi.c >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c >> @@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) >> >> /* Program Tx latency optimal setting */ >> for (i = 0; i < 4; i++) { >> - /* Set the latency optimal bit */ >> - data = (i == 1) ? 0x0 : 0x6; >> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), >> - data << DPIO_FRC_LATENCY_SHFIT); >> - >> /* Set the upar bit */ >> data = (i == 1) ? 0x0 : 0x1; >> vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), >> -- >> 1.7.9.5 > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6167
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB -31 313/313 282/313
IVB 337/337 337/337
BYT 286/286 286/286
HSW 395/395 395/395
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
SNB igt@kms_flip@bo-too-big-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip_event_leak DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@nonexisting-fb DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@nonexisting-fb-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_flip_tiling@flip-changes-tiling DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@kms_rotation_crc@primary-rotation DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@cursor DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@cursor-dpms DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@debugfs-forcewake-user DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@dpms-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@drm-resources-equal DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@fences DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@fences-dpms DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@gem-execbuf DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@gem-idle DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@gem-mmap-cpu DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@gem-mmap-gtt DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@gem-pread DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@i2c DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@modeset-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@pci-d3-state DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@reg-read-ioctl DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
SNB igt@pm_rpm@rte DMESG_WARN(5)PASS(3) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
Note: You need to pay more attention to line start with '*'
On Sat, 11 Apr 2015, shuang.he@intel.com wrote: > Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) > Task id: 6167 > -------------------------------------Summary------------------------------------- > Platform Delta drm-intel-nightly Series Applied > PNV 276/276 276/276 > ILK 302/302 302/302 > SNB -31 313/313 282/313 The patch does not touch SNB code paths, what gives? BR, Jani. > IVB 337/337 337/337 > BYT 286/286 286/286 > HSW 395/395 395/395 > BDW 321/321 321/321 > -------------------------------------Detailed------------------------------------- > Platform Test drm-intel-nightly Series Applied > SNB igt@kms_flip@bo-too-big-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip_event_leak DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@nonexisting-fb DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@nonexisting-fb-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_flip_tiling@flip-changes-tiling DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@kms_rotation_crc@primary-rotation DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@cursor DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@cursor-dpms DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@debugfs-forcewake-user DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@dpms-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@drm-resources-equal DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@fences DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@fences-dpms DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@gem-execbuf DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@gem-idle DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@gem-mmap-cpu DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@gem-mmap-gtt DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@gem-pread DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@i2c DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@modeset-non-lpsp DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@pci-d3-state DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@reg-read-ioctl DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > SNB igt@pm_rpm@rte DMESG_WARN(5)PASS(3) DMESG_WARN(2) > (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up > drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting > Note: You need to pay more attention to line start with '*' > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Apr 13, 2015 at 02:04:27PM +0300, Jani Nikula wrote: > On Sat, 11 Apr 2015, shuang.he@intel.com wrote: > > Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) > > Task id: 6167 > > -------------------------------------Summary------------------------------------- > > Platform Delta drm-intel-nightly Series Applied > > PNV 276/276 276/276 > > ILK 302/302 302/302 > > SNB -31 313/313 282/313 > > The patch does not touch SNB code paths, what gives? In the past few days dp link retraining sprung up all over the place in PRTS results. I dunno what exactly is happening. I think He Shuang is still investigating. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b87969..f106763 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2740,11 +2740,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) /* Program Tx lane latency optimal setting*/ for (i = 0; i < 4; i++) { - /* Set the latency optimal bit */ - data = (i == 1) ? 0x0 : 0x6; - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), - data << DPIO_FRC_LATENCY_SHFIT); - /* Set the upar bit */ data = (i == 1) ? 0x0 : 0x1; vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 26222e6..3cef326 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) /* Program Tx latency optimal setting */ for (i = 0; i < 4; i++) { - /* Set the latency optimal bit */ - data = (i == 1) ? 0x0 : 0x6; - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), - data << DPIO_FRC_LATENCY_SHFIT); - /* Set the upar bit */ data = (i == 1) ? 0x0 : 0x1; vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),