| Message ID | 1428679293-6208-6-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Friday 10 April 2015 08:51 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Currently vlv_wait_port_ready() waits for all four lanes on the > appropriate channel. This no longer works on CHV when the unused > lanes may be power gated. So pass in a mask of lanes that the > caller is expecting to be ready. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 10 ++++++---- > drivers/gpu/drm/i915/intel_dp.c | 4 +++- > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- > 4 files changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 7bfe2af..2aa8055 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1819,7 +1819,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > } > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > - struct intel_digital_port *dport) > + struct intel_digital_port *dport, > + unsigned int expected_mask) > { > u32 port_mask; > int dpll_reg; > @@ -1832,6 +1833,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > case PORT_C: > port_mask = DPLL_PORTC_READY_MASK; > dpll_reg = DPLL(0); > + expected_mask <<= 4; > break; > case PORT_D: > port_mask = DPLL_PORTD_READY_MASK; > @@ -1841,9 +1843,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > BUG(); > } > > - if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) > - WARN(1, "timed out waiting for port %c ready: 0x%08x\n", > - port_name(dport->port), I915_READ(dpll_reg)); > + if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) > + WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", > + port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); > } > > static void intel_prepare_shared_dpll(struct intel_crtc *crtc) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 7401fa3..ac38fd8 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2472,6 +2472,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > uint32_t dp_reg = I915_READ(intel_dp->output_reg); > + unsigned int lane_mask = 0x0; > > if (WARN_ON(dp_reg & DP_PORT_EN)) > return; > @@ -2490,7 +2491,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) > pps_unlock(intel_dp); > > if (IS_VALLEYVIEW(dev)) > - vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); > + vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), > + lane_mask); > > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > intel_dp_start_link_train(intel_dp); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index efa53d5..3ec829a 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -951,7 +951,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) > } > int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > - struct intel_digital_port *dport); > + struct intel_digital_port *dport, > + unsigned int expected_mask); > bool intel_get_load_detect_pipe(struct drm_connector *connector, > struct drm_display_mode *mode, > struct intel_load_detect_pipe *old, > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index a24e2c8..24b0aa1 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1319,7 +1319,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) > > intel_enable_hdmi(encoder); > > - vlv_wait_port_ready(dev_priv, dport); > + vlv_wait_port_ready(dev_priv, dport, 0x0); > } > > static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) > @@ -1636,7 +1636,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) > > intel_enable_hdmi(encoder); > > - vlv_wait_port_ready(dev_priv, dport); > + vlv_wait_port_ready(dev_priv, dport, 0x0); > } > > static void intel_hdmi_destroy(struct drm_connector *connector) Looks good. Reviewed-by: Deepak S<deepak.s@linux.intel.com>
On Fri, May 08, 2015 at 07:23:42PM +0530, Deepak S wrote: > > > On Friday 10 April 2015 08:51 PM, ville.syrjala@linux.intel.com wrote: > >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > >Currently vlv_wait_port_ready() waits for all four lanes on the > >appropriate channel. This no longer works on CHV when the unused > >lanes may be power gated. So pass in a mask of lanes that the > >caller is expecting to be ready. > > > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >--- > > drivers/gpu/drm/i915/intel_display.c | 10 ++++++---- > > drivers/gpu/drm/i915/intel_dp.c | 4 +++- > > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > > drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- > > 4 files changed, 13 insertions(+), 8 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >index 7bfe2af..2aa8055 100644 > >--- a/drivers/gpu/drm/i915/intel_display.c > >+++ b/drivers/gpu/drm/i915/intel_display.c > >@@ -1819,7 +1819,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > > } > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > >- struct intel_digital_port *dport) > >+ struct intel_digital_port *dport, > >+ unsigned int expected_mask) > > { > > u32 port_mask; > > int dpll_reg; > >@@ -1832,6 +1833,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > > case PORT_C: > > port_mask = DPLL_PORTC_READY_MASK; > > dpll_reg = DPLL(0); > >+ expected_mask <<= 4; > > break; > > case PORT_D: > > port_mask = DPLL_PORTD_READY_MASK; > >@@ -1841,9 +1843,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > > BUG(); > > } > >- if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) > >- WARN(1, "timed out waiting for port %c ready: 0x%08x\n", > >- port_name(dport->port), I915_READ(dpll_reg)); > >+ if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) > >+ WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", > >+ port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); > > } > > static void intel_prepare_shared_dpll(struct intel_crtc *crtc) > >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >index 7401fa3..ac38fd8 100644 > >--- a/drivers/gpu/drm/i915/intel_dp.c > >+++ b/drivers/gpu/drm/i915/intel_dp.c > >@@ -2472,6 +2472,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) > > struct drm_i915_private *dev_priv = dev->dev_private; > > struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); > > uint32_t dp_reg = I915_READ(intel_dp->output_reg); > >+ unsigned int lane_mask = 0x0; > > if (WARN_ON(dp_reg & DP_PORT_EN)) > > return; > >@@ -2490,7 +2491,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) > > pps_unlock(intel_dp); > > if (IS_VALLEYVIEW(dev)) > >- vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); > >+ vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), > >+ lane_mask); > > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > > intel_dp_start_link_train(intel_dp); > >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >index efa53d5..3ec829a 100644 > >--- a/drivers/gpu/drm/i915/intel_drv.h > >+++ b/drivers/gpu/drm/i915/intel_drv.h > >@@ -951,7 +951,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) > > } > > int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > >- struct intel_digital_port *dport); > >+ struct intel_digital_port *dport, > >+ unsigned int expected_mask); > > bool intel_get_load_detect_pipe(struct drm_connector *connector, > > struct drm_display_mode *mode, > > struct intel_load_detect_pipe *old, > >diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > >index a24e2c8..24b0aa1 100644 > >--- a/drivers/gpu/drm/i915/intel_hdmi.c > >+++ b/drivers/gpu/drm/i915/intel_hdmi.c > >@@ -1319,7 +1319,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) > > intel_enable_hdmi(encoder); > >- vlv_wait_port_ready(dev_priv, dport); > >+ vlv_wait_port_ready(dev_priv, dport, 0x0); > > } > > static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) > >@@ -1636,7 +1636,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) > > intel_enable_hdmi(encoder); > >- vlv_wait_port_ready(dev_priv, dport); > >+ vlv_wait_port_ready(dev_priv, dport, 0x0); > > } > > static void intel_hdmi_destroy(struct drm_connector *connector) > > Looks good. > Reviewed-by: Deepak S<deepak.s@linux.intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7bfe2af..2aa8055 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1819,7 +1819,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport) + struct intel_digital_port *dport, + unsigned int expected_mask) { u32 port_mask; int dpll_reg; @@ -1832,6 +1833,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, case PORT_C: port_mask = DPLL_PORTC_READY_MASK; dpll_reg = DPLL(0); + expected_mask <<= 4; break; case PORT_D: port_mask = DPLL_PORTD_READY_MASK; @@ -1841,9 +1843,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, BUG(); } - if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) - WARN(1, "timed out waiting for port %c ready: 0x%08x\n", - port_name(dport->port), I915_READ(dpll_reg)); + if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) + WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", + port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); } static void intel_prepare_shared_dpll(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7401fa3..ac38fd8 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2472,6 +2472,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); uint32_t dp_reg = I915_READ(intel_dp->output_reg); + unsigned int lane_mask = 0x0; if (WARN_ON(dp_reg & DP_PORT_EN)) return; @@ -2490,7 +2491,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) pps_unlock(intel_dp); if (IS_VALLEYVIEW(dev)) - vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); + vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), + lane_mask); intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index efa53d5..3ec829a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -951,7 +951,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) } int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport); + struct intel_digital_port *dport, + unsigned int expected_mask); bool intel_get_load_detect_pipe(struct drm_connector *connector, struct drm_display_mode *mode, struct intel_load_detect_pipe *old, diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index a24e2c8..24b0aa1 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1319,7 +1319,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) intel_enable_hdmi(encoder); - vlv_wait_port_ready(dev_priv, dport); + vlv_wait_port_ready(dev_priv, dport, 0x0); } static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) @@ -1636,7 +1636,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) intel_enable_hdmi(encoder); - vlv_wait_port_ready(dev_priv, dport); + vlv_wait_port_ready(dev_priv, dport, 0x0); } static void intel_hdmi_destroy(struct drm_connector *connector)