From patchwork Thu Apr 23 12:28:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sonika.jindal@intel.com X-Patchwork-Id: 6262081 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A37ABF4A6 for ; Thu, 23 Apr 2015 12:37:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BAD60202EC for ; Thu, 23 Apr 2015 12:37:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BE254200DF for ; Thu, 23 Apr 2015 12:37:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A7D56E777; Thu, 23 Apr 2015 05:37:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F3866E777 for ; Thu, 23 Apr 2015 05:37:17 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP; 23 Apr 2015 05:37:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,630,1422950400"; d="scan'208";a="560632433" Received: from sonikaji-desktop.iind.intel.com ([10.223.25.81]) by orsmga003.jf.intel.com with ESMTP; 23 Apr 2015 05:37:14 -0700 From: Sonika Jindal To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Apr 2015 17:58:30 +0530 Message-Id: <1429792110-5663-1-git-send-email-sonika.jindal@intel.com> X-Mailer: git-send-email 1.7.10.4 Subject: [Intel-gfx] [PATCH] drm/i915/skl: Select DDIA lane capability based upon vbt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, if bios fails to drive an edp panel due to any reason, the ddi buffer will not be enabled. And the DDIA lane capability will remain 0. This leads to assumption of DDIA x2 which means DDIA supports 2 lanes and DDIE supports 2 lanes. For some higher resolution panel which needs 4 lanes, we end up using only 2 lanes which doesn't let the modeset go through because of limited data rate avalaible. So, set the DDIA lane capability correctly if port E is being used by any child device or not. Cc: Sivakumar Thulasimani Signed-off-by: Sonika Jindal Reviewed-by: Sivakumar Thulasimani Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 4 ++++ drivers/gpu/drm/i915/intel_bios.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++ 4 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 79da7f3..9aad54b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1384,6 +1384,7 @@ struct intel_vbt_data { union child_device_config *child_dev; struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; + unsigned int ddi_e_used; }; enum intel_ddb_partitioning { diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c08368c..16c5885 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1119,6 +1119,9 @@ parse_device_mapping(struct drm_i915_private *dev_priv, dev_priv->vbt.dsi.port = p_child->common.dvo_port; } + if (p_child->common.dvo_port == DVO_PORT_DPE) + dev_priv->vbt.ddi_e_used = 1; + child_dev_ptr = dev_priv->vbt.child_dev + count; count++; memcpy((void *)child_dev_ptr, (void *)p_child, @@ -1169,6 +1172,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv) info->supports_hdmi = info->supports_dvi; info->supports_dp = (port != PORT_E); } + dev_priv->vbt.ddi_e_used = 0; } static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index af0b476..dd85812 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -764,6 +764,7 @@ int intel_parse_bios(struct drm_device *dev); #define DVO_PORT_DPC 8 #define DVO_PORT_DPD 9 #define DVO_PORT_DPA 10 +#define DVO_PORT_DPE 11 #define DVO_PORT_MIPIA 21 #define DVO_PORT_MIPIB 22 #define DVO_PORT_MIPIC 23 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b974f8e..c8e370a 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2139,6 +2139,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) struct intel_encoder *intel_encoder; struct drm_encoder *encoder; bool init_hdmi, init_dp; + int val; init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || dev_priv->vbt.ddi_port_info[port].supports_hdmi); @@ -2169,6 +2170,13 @@ void intel_ddi_init(struct drm_device *dev, enum port port) intel_encoder->get_config = intel_ddi_get_config; intel_dig_port->port = port; + + val = I915_READ(DDI_BUF_CTL(port)); + if (IS_SKYLAKE(dev) && port == PORT_A + && !(val & DDI_BUF_CTL_ENABLE) + && !dev_priv->vbt.ddi_e_used) + I915_WRITE(DDI_BUF_CTL(port), val | DDI_A_4_LANES); + intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);