| Message ID | 1430288260-23718-3-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> On 4/29/2015 11:47 AM, Mika Kahola wrote: > This patch adds DP link training optimization by reusing the > previously trained values. > > v2: > - rebase > > V3: > - rebase > > V4: > - when HPD long pulse is received, the flag is cleared > that indicates if DP link training is required or not > (based on Sivakumar's comment) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index e0b35cb..bb1a8d0 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) > intel_dp->DP = DP; > > if (channel_eq) { > - intel_dp->train_set_valid = is_edp(intel_dp); > + intel_dp->train_set_valid = true; > DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); > } > } > @@ -4843,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > intel_display_power_get(dev_priv, power_domain); > > if (long_hpd) { > + /* indicate that we need to restart link training */ > + intel_dp->train_set_valid = false; > > if (HAS_PCH_SPLIT(dev)) { > if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6284
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 316/316 316/316
IVB 264/264 264/264
BYT -4 227/227 223/227
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(8) TIMEOUT(1)PASS(1)
*BYT igt@gem_exec_parse@chained-batch FAIL(1)PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found
WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(4)PASS(5) TIMEOUT(2)
*BYT igt@gem_userptr_blits@forked-unsync-interruptible FAIL(1)PASS(2) DMESG_WARN(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found
WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index e0b35cb..bb1a8d0 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) intel_dp->DP = DP; if (channel_eq) { - intel_dp->train_set_valid = is_edp(intel_dp); + intel_dp->train_set_valid = true; DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); } } @@ -4843,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) intel_display_power_get(dev_priv, power_domain); if (long_hpd) { + /* indicate that we need to restart link training */ + intel_dp->train_set_valid = false; if (HAS_PCH_SPLIT(dev)) { if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase V3: - rebase V4: - when HPD long pulse is received, the flag is cleared that indicates if DP link training is required or not (based on Sivakumar's comment) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)