From patchwork Wed Apr 29 22:13:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yu.dai@intel.com X-Patchwork-Id: 6298721 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 16E8B9F373 for ; Wed, 29 Apr 2015 22:15:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00C95201C8 for ; Wed, 29 Apr 2015 22:15:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F23582017D for ; Wed, 29 Apr 2015 22:15:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F00D46E73F; Wed, 29 Apr 2015 15:15:21 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 9814B6E731 for ; Wed, 29 Apr 2015 15:15:15 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 29 Apr 2015 15:15:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,672,1422950400"; d="scan'208";a="721303734" Received: from alex-hsw.fm.intel.com ([10.19.123.33]) by orsmga002.jf.intel.com with ESMTP; 29 Apr 2015 15:15:15 -0700 From: yu.dai@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Apr 2015 15:13:33 -0700 Message-Id: <1430345615-5576-13-git-send-email-yu.dai@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430345615-5576-1-git-send-email-yu.dai@intel.com> References: <1430345615-5576-1-git-send-email-yu.dai@intel.com> Subject: [Intel-gfx] [PATCH v6 12/14] drm/i915: debugfs of GuC status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Dai Now print out Bootrom, uKernel and MIA Core status. The scratch reg 0 & 15 are used for communication between driver and firmware. Their status is also printed out. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_debugfs.c | 79 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 13 ++++++ drivers/gpu/drm/i915/intel_guc_client.c | 33 +++++++++++--- 3 files changed, 118 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9c2b9e4..f12bbee 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2310,6 +2310,83 @@ static int i915_llc(struct seq_file *m, void *data) return 0; } +static void i915_uc_load_status_info(struct seq_file *m, struct intel_uc_fw *uc_fw) +{ + seq_printf(m, "%s firmware status:\n\tpath: <%s>\n\tfetch: %d\n\tload: %d\n", + uc_fw->uc_name, + uc_fw->uc_fw_path, + uc_fw->uc_fw_fetch_status, + uc_fw->uc_fw_load_status); +} + +static int i915_guc_load_status_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = m->private; + struct drm_i915_private *dev_priv = node->minor->dev->dev_private; + u32 tmp, i; + + if (!HAS_GUC_UCODE(dev_priv->dev)) + return 0; + + i915_uc_load_status_info(m, &dev_priv->guc.guc_fw); + + tmp = I915_READ(GUC_STATUS); + + seq_puts(m, "\nResponse from GuC:\n"); + seq_printf(m, "\tBootrom status = 0x%x\n", + (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); + seq_printf(m, "\tuKernel status = 0x%x\n", + (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); + seq_printf(m, "\tMIA Core status = 0x%x\n", + (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); + seq_puts(m, "Scratch registers value:\n"); + for (i = 0; i < 16; i++) + seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); + + return 0; +} + +static int i915_guc_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = m->private; + struct drm_device *dev = node->minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_guc guc; + struct i915_guc_client client; + + if (!i915.enable_guc_scheduling) + return 0; + + memset(&client, 0, sizeof(struct i915_guc_client)); + + /* Take a local copy of the GuC data, so we can dump it at leisure */ + spin_lock(&dev_priv->guc.host2guc_lock); + guc = dev_priv->guc; + if (guc.execbuf_client) { + spin_lock(&guc.execbuf_client->wq_lock); + client = *guc.execbuf_client; + spin_unlock(&guc.execbuf_client->wq_lock); + } + spin_unlock(&dev_priv->guc.host2guc_lock); + + seq_printf(m, "GuC total action count: %llu\n", guc.action_count); + seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); + seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); + + seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); + seq_printf(m, "GuC last action error code: %d\n", guc.action_err); + + seq_printf(m, "GuC execbuf client @ %p:\n", guc.execbuf_client); + seq_printf(m, "\tTotal submissions: %llu\n", client.submissions); + seq_printf(m, "\tFailed to queue: %u\n", client.q_fail); + seq_printf(m, "\tFailed doorbell: %u\n", client.b_fail); + seq_printf(m, "\tLast submission result: %d\n", client.retcode); + + /* Add more as required ... */ + + return 0; +} + static int i915_edp_psr_status(struct seq_file *m, void *data) { struct drm_info_node *node = m->private; @@ -4776,6 +4853,8 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, + {"i915_guc_info", i915_guc_info, 0}, + {"i915_guc_load_status", i915_guc_load_status_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, {"i915_drpc_info", i915_drpc_info, 0}, diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index f8065cf..b096d1a 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -42,6 +42,12 @@ struct i915_guc_client { uint32_t wq_size; uint32_t wq_tail; uint32_t cookie; + + /* GuC submission statistics & status */ + uint64_t submissions; + uint32_t q_fail; + uint32_t b_fail; + int retcode; }; #define I915_MAX_DOORBELLS 256 @@ -66,6 +72,13 @@ struct intel_guc { struct ida ctx_ids; int db_cacheline; DECLARE_BITMAP(doorbell_bitmap, I915_MAX_DOORBELLS); + + /* Action status & statistics */ + uint64_t action_count; /* Total commands issued */ + uint32_t action_cmd; /* Last command word */ + uint32_t action_status; /* Last return status */ + uint32_t action_fail; /* Total number of failures */ + int32_t action_err; /* Last error code */ }; #define GUC_STATUS 0xc000 diff --git a/drivers/gpu/drm/i915/intel_guc_client.c b/drivers/gpu/drm/i915/intel_guc_client.c index 31934a3..adfff1c 100644 --- a/drivers/gpu/drm/i915/intel_guc_client.c +++ b/drivers/gpu/drm/i915/intel_guc_client.c @@ -87,6 +87,9 @@ static int intel_guc_action(struct intel_guc *guc, u32 *data, u32 len) spin_lock(&dev_priv->guc.host2guc_lock); + dev_priv->guc.action_count += 1; + dev_priv->guc.action_cmd = data[0]; + for (i = 0; i < len; i++) I915_WRITE(SOFT_SCRATCH(i), data[i]); @@ -105,7 +108,11 @@ static int intel_guc_action(struct intel_guc *guc, u32 *data, u32 len) "status=0x%08X response=0x%08X\n", data[0], ret, status, I915_READ(SOFT_SCRATCH(15))); + + dev_priv->guc.action_fail += 1; + dev_priv->guc.action_err = ret; } + dev_priv->guc.action_status = status; spin_unlock(&dev_priv->guc.host2guc_lock); @@ -614,13 +621,25 @@ int i915_guc_client_submit(struct i915_guc_client *client, struct intel_context *ctx, struct intel_engine_cs *ring) { - int ret; - - ret = add_workqueue_item(client, ctx, ring); - if (ret) - return ret; + int q_ret, b_ret; + unsigned long flags; - ret = ring_doorbell(client); + q_ret = add_workqueue_item(client, ctx, ring); + if (q_ret == 0) + b_ret = ring_doorbell(client); + + spin_lock_irqsave(&client->wq_lock, flags); + client->submissions += 1; + if (q_ret) { + client->q_fail += 1; + client->retcode = q_ret; + } else if (b_ret) { + client->b_fail += 1; + client->retcode = q_ret = b_ret; + } else { + client->retcode = 0; + } + spin_unlock_irqrestore(&client->wq_lock, flags); - return ret; + return q_ret; }