From patchwork Wed Apr 29 22:13:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yu.dai@intel.com X-Patchwork-Id: 6298651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A4C48BEEE1 for ; Wed, 29 Apr 2015 22:15:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71F5F20154 for ; Wed, 29 Apr 2015 22:15:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7AB3A2013A for ; Wed, 29 Apr 2015 22:15:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0047E6E72B; Wed, 29 Apr 2015 15:15:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 47BB46E736 for ; Wed, 29 Apr 2015 15:15:10 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 29 Apr 2015 15:15:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,672,1422950400"; d="scan'208";a="721303675" Received: from alex-hsw.fm.intel.com ([10.19.123.33]) by orsmga002.jf.intel.com with ESMTP; 29 Apr 2015 15:15:10 -0700 From: yu.dai@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Apr 2015 15:13:28 -0700 Message-Id: <1430345615-5576-8-git-send-email-yu.dai@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430345615-5576-1-git-send-email-yu.dai@intel.com> References: <1430345615-5576-1-git-send-email-yu.dai@intel.com> Subject: [Intel-gfx] [PATCH v6 07/14] drm/i915: Add functions to allocate / release gem obj for GuC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Dai All gem objects used by GuC are pinned to ggtt space out of range [0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is used internally for its Boot ROM, SRAM etc. Currently this WPOCM size is 512K. This is done by using of PIN_OFFSET_BIAS. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_guc.h | 3 ++ drivers/gpu/drm/i915/intel_guc_loader.c | 55 +++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index c6886d1..3082a3e 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -102,5 +102,8 @@ struct intel_guc { extern int intel_guc_ucode_load(struct drm_device *dev, bool wait); extern void intel_guc_ucode_fini(struct drm_device *dev); extern void intel_guc_ucode_init(struct drm_device *dev); +struct drm_i915_gem_object * +intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size); +void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj); #endif diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 0f13620..49f3730 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -45,6 +45,12 @@ * The firmware installation package will install (symbolic link) proper version * of firmware. * + * GuC address space: + * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), + * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is + * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects + * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. + * */ #define I915_SKL_GUC_UCODE "i915/skl_guc_ver1.bin" @@ -52,6 +58,55 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE); #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver1.bin" MODULE_FIRMWARE(I915_BXT_GUC_UCODE); +/** + * intel_guc_allocate_gem_obj() - Allocate gem object for GuC usage + * @dev: drm device + * @size: size of object + * + * This is a wrapper to create a gem obj. In order to use it inside GuC, the + * object needs to be pinned lifetime. Also we must pin it to gtt space other + * than [0, GUC_WOPCM_SIZE] because this range is reserved inside GuC. + * + * Return: A drm_i915_gem_object if successful, otherwise NULL. + */ +struct drm_i915_gem_object * +intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size) +{ + struct drm_i915_gem_object *obj; + + obj = i915_gem_alloc_object(dev, size); + if (!obj) + return NULL; + + if (i915_gem_object_get_pages(obj)) { + drm_gem_object_unreference(&obj->base); + return NULL; + } + + if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, + PIN_OFFSET_BIAS | GUC_WOPCM_SIZE_VALUE)) { + drm_gem_object_unreference(&obj->base); + return NULL; + } + + return obj; +} + +/** + * intel_guc_release_gem_obj() - Release gem object allocated for GuC usage + * @obj: gem obj to be released + */ +void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj) +{ + if (!obj) + return; + + if (i915_gem_obj_is_pinned(obj)) + i915_gem_object_ggtt_unpin(obj); + + drm_gem_object_unreference(&obj->base); +} + /* Read GuC status register (GUC_STATUS) * Return true if get a success code from normal boot or RC6 boot */