| Message ID | 1430825455-28382-1-git-send-email-akash.goel@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 5, 2015 at 4:30 AM, <akash.goel@intel.com> wrote: > From: Akash Goel <akash.goel@intel.com> > > Read the efficient frequency (aka RPe) value through the the mailbox > command (0x1A) from the pcode, as done on Haswell and Broadwell. > The turbo minimum frequency softlimit is not revised as per the > efficient frequency value. > > Issue: VIZ-5143 > Signed-off-by: Akash Goel <akash.goel@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a7516ed..421b78d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4274,16 +4274,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { Could you please give me a pointer in the spec to this? Couldn't find on new one. > ret = sandybridge_pcode_read(dev_priv, > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > &ddcc_status); > - if (0 == ret) > + if (0 == ret) { > dev_priv->rps.efficient_freq = > clamp_t(u8, > ((ddcc_status >> 8) & 0xff), > dev_priv->rps.min_freq, > dev_priv->rps.max_freq); > + > + dev_priv->rps.efficient_freq *= > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); I thought you were managing everything on 50MHz and converting to 16.6 only when writing. So this here seems to me that will compare to values in different bases.. > + } > } > > dev_priv->rps.idle_freq = dev_priv->rps.min_freq; > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 2015-06-03 at 14:19 -0700, Rodrigo Vivi wrote: > On Tue, May 5, 2015 at 4:30 AM, <akash.goel@intel.com> wrote: > > From: Akash Goel <akash.goel@intel.com> > > > > Read the efficient frequency (aka RPe) value through the the mailbox > > command (0x1A) from the pcode, as done on Haswell and Broadwell. > > The turbo minimum frequency softlimit is not revised as per the > > efficient frequency value. > > > > Issue: VIZ-5143 > > Signed-off-by: Akash Goel <akash.goel@intel.com> > > --- > > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index a7516ed..421b78d 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4274,16 +4274,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { > > Could you please give me a pointer in the spec to this? Couldn't find > on new one. Actually got this piece of info from fellow VPG engineers. Sorry I myself don't have the access to the Punit spec. > > ret = sandybridge_pcode_read(dev_priv, > > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > > &ddcc_status); > > - if (0 == ret) > > + if (0 == ret) { > > dev_priv->rps.efficient_freq = > > clamp_t(u8, > > ((ddcc_status >> 8) & 0xff), > > dev_priv->rps.min_freq, > > dev_priv->rps.max_freq); > > + > > + dev_priv->rps.efficient_freq *= > > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > > I thought you were managing everything on 50MHz and converting to 16.6 > only when writing. So this here seems to me that will compare to > values in different bases.. The frequency values are being internally maintained in their natural hardware units only (and functions intel_gpu_freq & intel_freq_opcode help in the conversion). For SKL, although unit is 16.667 MHz, but there are few exceptions like RP_STATE register, which still reports frequency in 50 MHZ units, so an extra conversion is required there to internally store the values in 16.667 MHZ. The Ring frequency table programming is another instance where update has to be done as per 50 MHZ unit. Best regards Akash > > > + } > > } > > > > dev_priv->rps.idle_freq = dev_priv->rps.min_freq; > > -- > > 1.9.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a7516ed..421b78d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4274,16 +4274,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { ret = sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status); - if (0 == ret) + if (0 == ret) { dev_priv->rps.efficient_freq = clamp_t(u8, ((ddcc_status >> 8) & 0xff), dev_priv->rps.min_freq, dev_priv->rps.max_freq); + + dev_priv->rps.efficient_freq *= + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + } } dev_priv->rps.idle_freq = dev_priv->rps.min_freq;