| Message ID | 1430987368-31740-1-git-send-email-sonika.jindal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 07 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote: > The sink rate read from supported link rate table is in KHz as per spec > while in drm, the saved clock is in deca-KHz. So divide the link rate by > 10 before storing. > > Reading of rates was added by: > commit fc0f8e25318f ("drm/i915/skl: Read sink supported rates from edp > panel") Thanks; now this git spell $ git tag --contains fc0f8e25318f | grep ^v[0-9] | sort -V | head -n 1 v4.1-rc1 will tell me I need to queue this one to v4.1 through drm-intel-fixes while the rest is for Daniel to merge to drm-intel-next-queued. Pushed, thanks for the patch and review. BR, Jani. > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index bacdec5..6bd5afb 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > if (val == 0) > break; > > - intel_dp->sink_rates[i] = val * 200; > + /* Value read is in kHz while drm clock is saved in deca-kHz */ > + intel_dp->sink_rates[i] = (val * 200) / 10; > } > intel_dp->num_sink_rates = i; > } > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bacdec5..6bd5afb 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) if (val == 0) break; - intel_dp->sink_rates[i] = val * 200; + /* Value read is in kHz while drm clock is saved in deca-kHz */ + intel_dp->sink_rates[i] = (val * 200) / 10; } intel_dp->num_sink_rates = i; }
The sink rate read from supported link rate table is in KHz as per spec while in drm, the saved clock is in deca-KHz. So divide the link rate by 10 before storing. Reading of rates was added by: commit fc0f8e25318f ("drm/i915/skl: Read sink supported rates from edp panel") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)