From patchwork Mon May 11 07:51:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 6373771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B81859F32E for ; Mon, 11 May 2015 07:52:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D7854202EC for ; Mon, 11 May 2015 07:52:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 053CC202E9 for ; Mon, 11 May 2015 07:52:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85F5F6E2DA; Mon, 11 May 2015 00:52:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from relay.fireflyinternet.com (hostedrelay.fireflyinternet.com [109.228.30.76]) by gabe.freedesktop.org (Postfix) with ESMTP id B39516E2DA for ; Mon, 11 May 2015 00:51:58 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by relay.fireflyinternet.com (FireflyRelay1) with ESMTP id 596471-1305619 for multiple; Mon, 11 May 2015 08:51:39 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 May 2015 08:51:36 +0100 Message-Id: <1431330696-15379-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.1.4 X-Authenticated-User: chris.alporthouse@surfanytime.net Cc: Akash Goel , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915: Unconditionally flush writes before execbuffer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With the advent of mmap(wc), we have a path to write directly into active GPU buffers. When combined with async updates (i.e. avoiding the explicit domain management along with the memory barriers and GPU stalls) we start to see the GPU read the wrong values from memory - i.e. we have insufficient memory barriers along the execbuffer path. Writes through the GTT should have been naturally serialised with execution through the GTT as well and so the impact only seems to be from the WC paths. Signed-off-by: Chris Wilson Cc: Akash Goel Cc: stable@vger.kernel.org Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 650ae02484b0..4f97275ba799 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1127,8 +1127,12 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, if (flush_chipset) i915_gem_chipset_flush(ring->dev); - if (flush_domains & I915_GEM_DOMAIN_GTT) - wmb(); + /* Unconditionally flush out writes to memory as the user may be + * doing asynchronous streaming writes to active buffers (i.e. + * lazy domain management to avoid serialisation) directly into + * the physical pages and so not naturally serialised by the GTT. + */ + wmb(); /* Unconditionally invalidate gpu caches and ensure that we do flush * any residual writes from the previous batch.