From patchwork Wed May 13 16:40:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 6398781 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4C83F9F1C2 for ; Wed, 13 May 2015 16:40:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 64F412037E for ; Wed, 13 May 2015 16:40:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 44936202B4 for ; Wed, 13 May 2015 16:40:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 353D46E0EB; Wed, 13 May 2015 09:40:52 -0700 (PDT) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id A065D6E0EB for ; Wed, 13 May 2015 09:40:50 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 13 May 2015 09:40:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,421,1427785200"; d="scan'208";a="694393972" Received: from tursulin-linux.isw.intel.com ([10.102.226.59]) by orsmga001.jf.intel.com with ESMTP; 13 May 2015 09:40:48 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 13 May 2015 17:40:44 +0100 Message-Id: <1431535244-8311-1-git-send-email-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.4.0 MIME-Version: 1.0 Cc: Ander Conselvan de Oliveira , Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,HK_RANDOM_FROM, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing dpll state and recomputing it via crtc_compute_clock (and probably some other commit which triggered pipe config checking), modesetting is now constantly triggering warnings about dpll_hw_state.ctrl1 mismatch. Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do anything for eDP, leaving the ctrl1 state at the default of zero. This potentially hacky fix makes skl_ddi_pll_select call skl_edp_set_pll_config which fixes the problem for me. Signed-off-by: Tvrtko Ursulin Cc: Damien Lespiau Cc: Ander Conselvan de Oliveira Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Ville Syrjälä Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- Big CC list so no one misses the chance of saying how this is not the right fix. :) But that is OK, I was just annoyed by the constant stream of warnings obscuring real problems. --- drivers/gpu/drm/i915/intel_ddi.c | 4 +++- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 807e15d..e5b7723 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1306,8 +1306,10 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, } cfgcr1 = cfgcr2 = 0; - } else /* eDP */ + } else /* eDP */ { + skl_edp_set_pll_config(crtc_state, clock); return true; + } crtc_state->dpll_hw_state.ctrl1 = ctrl1; crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 75bccd6..13b5b0e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1092,7 +1092,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector) intel_connector_unregister(intel_connector); } -static void +void skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) { u32 ctrl1; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index aa77af7..6e26644 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1193,6 +1193,9 @@ void intel_edp_drrs_invalidate(struct drm_device *dev, unsigned frontbuffer_bits); void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); +void +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock); + /* intel_dp_mst.c */ int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);