From patchwork Tue May 26 14:21:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 6482211 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EE1CA9F38C for ; Tue, 26 May 2015 14:21:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC71E20626 for ; Tue, 26 May 2015 14:21:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A0DAF20625 for ; Tue, 26 May 2015 14:21:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AAAC0720F3; Tue, 26 May 2015 07:21:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 848A9720F0 for ; Tue, 26 May 2015 07:21:37 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 26 May 2015 07:21:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,498,1427785200"; d="scan'208";a="715735084" Received: from michelth-linux.isw.intel.com ([10.102.226.66]) by fmsmga001.fm.intel.com with ESMTP; 26 May 2015 07:21:37 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Tue, 26 May 2015 15:21:24 +0100 Message-Id: <1432650084-24491-18-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.4.0 In-Reply-To: <1432650084-24491-1-git-send-email-michel.thierry@intel.com> References: <1432650084-24491-1-git-send-email-michel.thierry@intel.com> Cc: akash.goel@intel.com Subject: [Intel-gfx] [PATCH] tests/gem_ppgtt: Check Wa32bitOffsets workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Test EXEC_OBJECT_NEEDS_32BADDRESS flag to use reserved 32b segment. Driver will try to use lower PDPs of each PPGTT for the objects requiring Wa32bitGeneralStateOffset or Wa32bitInstructionBaseOffset. Signed-off-by: Michel Thierry --- tests/gem_ppgtt.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c index d1e484a..d70dcf9 100644 --- a/tests/gem_ppgtt.c +++ b/tests/gem_ppgtt.c @@ -48,7 +48,15 @@ #define HEIGHT 512 #define SIZE (HEIGHT*STRIDE) -static bool uses_full_ppgtt(int fd) +#define EXEC_OBJECT_NEEDS_32BADDR (1<<3) + +/* + * 0 - No PPGTT + * 1 - Aliasing PPGTT + * 2 - Full PPGTT (32b) + * 3 - Full PPGTT (48b) + */ +static bool __uses_full_ppgtt(int fd, int min) { struct drm_i915_getparam gp; int val = 0; @@ -61,7 +69,17 @@ static bool uses_full_ppgtt(int fd) return 0; errno = 0; - return val > 1; + return val >= min; +} + +static bool uses_full_ppgtt(int fd) +{ + return __uses_full_ppgtt(fd, 2); +} + +static bool uses_48b_full_ppgtt(int fd) +{ + return __uses_full_ppgtt(fd, 3); } static drm_intel_bo *create_bo(drm_intel_bufmgr *bufmgr, @@ -216,7 +234,7 @@ static void surfaces_check(dri_bo **bo, int count, uint32_t expected) } } -static uint64_t exec_and_get_offset(int fd, uint32_t batch) +static uint64_t exec_and_get_offset(int fd, uint32_t batch, bool needs_32b_addr) { struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_exec_object2 exec[1]; @@ -226,6 +244,7 @@ static uint64_t exec_and_get_offset(int fd, uint32_t batch) memset(exec, 0, sizeof(exec)); exec[0].handle = batch; + exec[0].flags = (needs_32b_addr) ? EXEC_OBJECT_NEEDS_32BADDR : 0; memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = (uintptr_t)exec; @@ -252,7 +271,7 @@ static void flink_and_close(void) fd2 = drm_open_any(); flinked_bo = gem_open(fd2, name); - offset = exec_and_get_offset(fd2, flinked_bo); + offset = exec_and_get_offset(fd2, flinked_bo, 0); gem_sync(fd2, flinked_bo); gem_close(fd2, flinked_bo); @@ -260,7 +279,7 @@ static void flink_and_close(void) * same size should get the same offset */ new_bo = gem_create(fd2, 4096); - offset_new = exec_and_get_offset(fd2, new_bo); + offset_new = exec_and_get_offset(fd2, new_bo, 0); gem_close(fd2, new_bo); igt_assert_eq(offset, offset_new); @@ -270,6 +289,64 @@ static void flink_and_close(void) close(fd2); } +static void createbo_and_compare_offsets(uint32_t fd, uint32_t fd2, + bool needs_32b, bool needs_32b2) +{ + uint32_t bo, bo2; + uint64_t offset, offset2; + + bo = gem_create(fd, 4096); + offset = exec_and_get_offset(fd, bo, needs_32b); + gem_sync(fd, bo); + + bo2 = gem_create(fd2, 4096); + offset2 = exec_and_get_offset(fd2, bo2, needs_32b2); + gem_sync(fd2, bo2); + + if (needs_32b == needs_32b2) + igt_assert_eq(offset, offset2); + else + igt_assert_neq(offset, offset2); + + + /* lower PDPs of each PPGTT are reserved for the objects + * requiring this workaround + */ + if (needs_32b) + igt_assert(offset < (1ULL << 32)); + + if (needs_32b2) + igt_assert(offset2 < (1ULL << 32)); + + gem_close(fd, bo); + gem_close(fd2, bo2); +} + + +static void wa_32b_offset_test(void) +{ + uint32_t fd, fd2; + + fd = drm_open_any(); + igt_require(uses_48b_full_ppgtt(fd)); + + fd2 = drm_open_any(); + + /* allow full addr range */ + createbo_and_compare_offsets(fd, fd2, 0, 0); + + /* limit 32b addr range */ + createbo_and_compare_offsets(fd, fd2, 1, 1); + + /* mixed */ + createbo_and_compare_offsets(fd, fd2, 0, 1); + createbo_and_compare_offsets(fd, fd2, 1, 0); + + close(fd); + close(fd2); +} + + #define N_CHILD 8 int main(int argc, char **argv) { @@ -302,5 +379,8 @@ int main(int argc, char **argv) igt_subtest("flink-and-close-vma-leak") flink_and_close(); + igt_subtest("wa-32b-offset-test") + wa_32b_offset_test(); + igt_exit(); }