From patchwork Wed May 27 07:05:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 6487791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E6C9FC0020 for ; Wed, 27 May 2015 07:05:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 12D46206F4 for ; Wed, 27 May 2015 07:05:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 13EA0206EF for ; Wed, 27 May 2015 07:05:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72A286E3B5; Wed, 27 May 2015 00:05:17 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 2424A6E3B5 for ; Wed, 27 May 2015 00:05:16 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 27 May 2015 00:05:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,502,1427785200"; d="scan'208";a="735901660" Received: from linux.intel.com ([10.23.219.25]) by orsmga002.jf.intel.com with ESMTP; 27 May 2015 00:05:15 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.237.72.59]) by linux.intel.com (Postfix) with ESMTP id A15E56A4005; Wed, 27 May 2015 00:04:42 -0700 (PDT) From: Ander Conselvan de Oliveira To: ville.syrjala@linux.intel.com Date: Wed, 27 May 2015 10:05:11 +0300 Message-Id: <1432710311-5745-1-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <20150402184249.GE17410@intel.com> References: <20150402184249.GE17410@intel.com> MIME-Version: 1.0 Cc: Ander Conselvan de Oliveira , intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: Include VLV in self refresh status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The line between maxfifo and SR is a blurry one. Since we treat them as the same thing, just read out the registers set up in intel_set_memory_cxsr(). References: https://bugs.freedesktop.org/show_bug.cgi?id=89792 Signed-off-by: Ander Conselvan de Oliveira --- On 04/02/2015 11:42 AM, Ville Syrjälä wrote: > On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote: >> I guess this is a lie for 8xx, but newer stuff takes care of this for >> us. >> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792 >> Signed-off-by: Jesse Barnes >> --- >> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >> b/drivers/gpu/drm/i915/i915_debugfs.c >> index 91c945b..a8f42a7 100644 >> --- a/drivers/gpu/drm/i915/i915_debugfs.c >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> @@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m, >> void *unused) >> sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; >> else if (IS_PINEVIEW(dev)) >> sr_enabled = I915_READ(DSPFW3) & >> PINEVIEW_SELF_REFRESH_EN; >> + else >> + sr_enabled = true; /* other platforms don't need >> enabling */ > > Not true actually. > > The line between maxfifo and SR is a blurry one. We treat them as the > same thing. So I think this should just read out whatever registers > we set up in intel_set_memory_cxsr(). Ville, does this patch does what you meant with the above sentence. I'm clueless about self-refresh, so I just paraphrased you in the commit message. Ander --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fece922..d80de9d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1731,6 +1731,8 @@ static int i915_sr_status(struct seq_file *m, void *unused) sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; else if (IS_PINEVIEW(dev)) sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + else if (IS_VALLEYVIEW(dev)) + sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; intel_runtime_pm_put(dev_priv);