| Message ID | 1433682144-11741-2-git-send-email-akash.goel@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
I have no access to this documentation, but overall it makes sense from the units I saw so feel free to use: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Sun, Jun 7, 2015 at 6:02 AM, <akash.goel@intel.com> wrote: > From: Akash Goel <akash.goel@intel.com> > > Read the efficient frequency (aka RPe) value through the the mailbox > command (0x1A) from the pcode, as done on Haswell and Broadwell. > The turbo minimum frequency softlimit is not revised as per the > efficient frequency value. > > Issue: VIZ-5143 > Signed-off-by: Akash Goel <akash.goel@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d091fec..1d14cce2 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4314,16 +4314,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { > ret = sandybridge_pcode_read(dev_priv, > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > &ddcc_status); > - if (0 == ret) > + if (0 == ret) { > dev_priv->rps.efficient_freq = > clamp_t(u8, > ((ddcc_status >> 8) & 0xff), > dev_priv->rps.min_freq, > dev_priv->rps.max_freq); > + > + dev_priv->rps.efficient_freq *= > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + } > } > > dev_priv->rps.idle_freq = dev_priv->rps.min_freq; > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > + > > + dev_priv->rps.efficient_freq *= > > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); This line seems awkward. I suppose a good compiler could optimize out the multiply by one. I would prefer something like: if(IS_SKYLAKE(dev)) dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; -- Tom O'Rourke
On Wed, 10 Jun 2015, "O'Rourke, Tom" <Tom.O'Rourke@intel.com> wrote: >> > + >> > + dev_priv->rps.efficient_freq *= >> > + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > > This line seems awkward. I suppose a good compiler could > optimize out the multiply by one. > > I would prefer something like: > > if(IS_SKYLAKE(dev)) > dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; Agreed, Jani. > > -- Tom O'Rourke > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d091fec..1d14cce2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4314,16 +4314,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { ret = sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status); - if (0 == ret) + if (0 == ret) { dev_priv->rps.efficient_freq = clamp_t(u8, ((ddcc_status >> 8) & 0xff), dev_priv->rps.min_freq, dev_priv->rps.max_freq); + + dev_priv->rps.efficient_freq *= + (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + } } dev_priv->rps.idle_freq = dev_priv->rps.min_freq;