diff mbox

[2/5] drm/i915/skl: Ring frequency table programming changes

Message ID 1433682144-11741-3-git-send-email-akash.goel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

akash.goel@intel.com June 7, 2015, 1:02 p.m. UTC 
From: Akash Goel <akash.goel@intel.com>

Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL

v2: Removed the check for avoiding ring frequency programming for BXT (Rodrigo)

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

Comments

Rodrigo Vivi June 9, 2015, 11:28 p.m. UTC | #1 
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Sun, Jun 7, 2015 at 6:02 AM,  <akash.goel@intel.com> wrote:
> From: Akash Goel <akash.goel@intel.com>
>
> Ring frequency table programming changes for SKL. No need for a
> floor on ring frequency, as the issue of performance impact with
> ring running below DDR frequency, is believed to be fixed on SKL
>
> v2: Removed the check for avoiding ring frequency programming for BXT (Rodrigo)

thanks

>
> Issue: VIZ-5144
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++----
>  1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1d14cce2..65938ea 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4622,6 +4622,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
>         int min_freq = 15;
>         unsigned int gpu_freq;
>         unsigned int max_ia_freq, min_ring_freq;
> +       unsigned int max_gpu_freq, min_gpu_freq;
>         int scaling_factor = 180;
>         struct cpufreq_policy *policy;
>
> @@ -4646,17 +4647,31 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
>         /* convert DDR frequency from units of 266.6MHz to bandwidth */
>         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>
> +       if (IS_SKYLAKE(dev)) {
> +               /* Convert GT frequency to 50 HZ units */
> +               min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
> +               max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
> +       } else {
> +               min_gpu_freq = dev_priv->rps.min_freq;
> +               max_gpu_freq = dev_priv->rps.max_freq;
> +       }
> +
>         /*
>          * For each potential GPU frequency, load a ring frequency we'd like
>          * to use for memory access.  We do this by specifying the IA frequency
>          * the PCU should use as a reference to determine the ring frequency.
>          */
> -       for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
> -            gpu_freq--) {
> -               int diff = dev_priv->rps.max_freq - gpu_freq;
> +       for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
> +               int diff = max_gpu_freq - gpu_freq;
>                 unsigned int ia_freq = 0, ring_freq = 0;
>
> -               if (INTEL_INFO(dev)->gen >= 8) {
> +               if (IS_SKYLAKE(dev)) {
> +                       /*
> +                        * ring_freq = 2 * GT. ring_freq is in 100MHz units
> +                        * No floor required for ring frequency on SKL.
> +                        */
> +                       ring_freq = gpu_freq;
> +               } else if (INTEL_INFO(dev)->gen >= 8) {
>                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
>                         ring_freq = max(min_ring_freq, gpu_freq);
>                 } else if (IS_HASWELL(dev)) {
> --
> 1.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1d14cce2..65938ea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4622,6 +4622,7 @@  static void __gen6_update_ring_freq(struct drm_device *dev)
 	int min_freq = 15;
 	unsigned int gpu_freq;
 	unsigned int max_ia_freq, min_ring_freq;
+	unsigned int max_gpu_freq, min_gpu_freq;
 	int scaling_factor = 180;
 	struct cpufreq_policy *policy;
 
@@ -4646,17 +4647,31 @@  static void __gen6_update_ring_freq(struct drm_device *dev)
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
+	if (IS_SKYLAKE(dev)) {
+		/* Convert GT frequency to 50 HZ units */
+		min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
+		max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
+	} else {
+		min_gpu_freq = dev_priv->rps.min_freq;
+		max_gpu_freq = dev_priv->rps.max_freq;
+	}
+
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
 	 * the PCU should use as a reference to determine the ring frequency.
 	 */
-	for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
-	     gpu_freq--) {
-		int diff = dev_priv->rps.max_freq - gpu_freq;
+	for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
+		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (INTEL_INFO(dev)->gen >= 8) {
+		if (IS_SKYLAKE(dev)) {
+			/*
+			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
+			 * No floor required for ring frequency on SKL.
+			 */
+			ring_freq = gpu_freq;
+		} else if (INTEL_INFO(dev)->gen >= 8) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev)) {