From patchwork Wed Jun 10 16:46:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 6583641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D2575C0020 for ; Wed, 10 Jun 2015 16:47:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DC55520398 for ; Wed, 10 Jun 2015 16:47:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CDB8F201DD for ; Wed, 10 Jun 2015 16:47:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C6617A0FF; Wed, 10 Jun 2015 09:47:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E829E7A0FF for ; Wed, 10 Jun 2015 09:47:28 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 10 Jun 2015 09:47:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,588,1427785200"; d="scan'208";a="708681385" Received: from michelth-linux.isw.intel.com ([10.102.226.66]) by orsmga001.jf.intel.com with ESMTP; 10 Jun 2015 09:47:04 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Wed, 10 Jun 2015 17:46:56 +0100 Message-Id: <1433954816-13787-20-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1433954816-13787-1-git-send-email-michel.thierry@intel.com> References: <1433954816-13787-1-git-send-email-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v2] tests/gem_ppgtt: Check Wa32bitOffsets workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Test I915_EXEC_SUPPORTS_48BADDRESS flag to use 32b+ segment. Driver will try to use lower PDPs of each PPGTT for the objects requiring Wa32bitGeneralStateOffset or Wa32bitInstructionBaseOffset. v2: Add flink cases, (suggested by Daniel Vetter). Signed-off-by: Michel Thierry --- tests/gem_ppgtt.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 147 insertions(+), 5 deletions(-) diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c index d1e484a..2471cf6 100644 --- a/tests/gem_ppgtt.c +++ b/tests/gem_ppgtt.c @@ -47,8 +47,18 @@ #define STRIDE (WIDTH*4) #define HEIGHT 512 #define SIZE (HEIGHT*STRIDE) +#define K (1024l) +#define M (1024l * K) +#define G (1024l * M) +#define LOCAL_EXEC_SUPPORT_48BADDRESS (1<<15) -static bool uses_full_ppgtt(int fd) +/* + * 0 - No PPGTT + * 1 - Aliasing PPGTT + * 2 - Full PPGTT (32b) + * 3 - Full PPGTT (48b) + */ +static bool __uses_full_ppgtt(int fd, int min) { struct drm_i915_getparam gp; int val = 0; @@ -61,7 +71,17 @@ static bool uses_full_ppgtt(int fd) return 0; errno = 0; - return val > 1; + return val >= min; +} + +static bool uses_full_ppgtt(int fd) +{ + return __uses_full_ppgtt(fd, 2); +} + +static bool uses_48b_full_ppgtt(int fd) +{ + return __uses_full_ppgtt(fd, 3); } static drm_intel_bo *create_bo(drm_intel_bufmgr *bufmgr, @@ -216,7 +236,7 @@ static void surfaces_check(dri_bo **bo, int count, uint32_t expected) } } -static uint64_t exec_and_get_offset(int fd, uint32_t batch) +static uint64_t exec_and_get_offset(int fd, uint32_t batch, bool needs_32b_addr) { struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_exec_object2 exec[1]; @@ -230,6 +250,7 @@ static uint64_t exec_and_get_offset(int fd, uint32_t batch) memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = (uintptr_t)exec; execbuf.buffer_count = 1; + execbuf.flags = (needs_32b_addr) ? 0 : LOCAL_EXEC_SUPPORT_48BADDRESS; gem_execbuf(fd, &execbuf); igt_assert_neq(exec[0].offset, -1); @@ -252,7 +273,7 @@ static void flink_and_close(void) fd2 = drm_open_any(); flinked_bo = gem_open(fd2, name); - offset = exec_and_get_offset(fd2, flinked_bo); + offset = exec_and_get_offset(fd2, flinked_bo, 0); gem_sync(fd2, flinked_bo); gem_close(fd2, flinked_bo); @@ -260,7 +281,7 @@ static void flink_and_close(void) * same size should get the same offset */ new_bo = gem_create(fd2, 4096); - offset_new = exec_and_get_offset(fd2, new_bo); + offset_new = exec_and_get_offset(fd2, new_bo, 0); gem_close(fd2, new_bo); igt_assert_eq(offset, offset_new); @@ -270,6 +291,124 @@ static void flink_and_close(void) close(fd2); } +static bool is_32b(uint64_t offset) +{ + return (offset < (1ULL << 32)); +} + +static void reusebo_and_compare_offsets(uint32_t fd, + uint64_t buf_size) +{ + uint32_t bo; + uint64_t offset, offset2; + + bo = gem_create(fd, buf_size); + /* support 48b addresses */ + offset = exec_and_get_offset(fd, bo, 0); + gem_sync(fd, bo); + + /* require 32b address */ + offset2 = exec_and_get_offset(fd, bo, 1); + gem_sync(fd, bo); + + igt_assert(is_32b(offset2)); + igt_assert_neq(offset, offset2); + gem_close(fd, bo); +} + +static void flinkbo_and_compare_offsets(uint32_t fd, uint32_t fd2, + uint64_t buf_size) +{ + uint32_t bo, flinked_bo, name; + uint64_t offset, offset2; + + bo = gem_create(fd, buf_size); + name = gem_flink(fd, bo); + + /* support 48b addresses */ + offset = exec_and_get_offset(fd, bo, 0); + gem_sync(fd, bo); + + /* require 32b address */ + flinked_bo = gem_open(fd2, name); + offset2 = exec_and_get_offset(fd2, flinked_bo, 1); + gem_sync(fd2, flinked_bo); + + igt_assert(is_32b(offset2)); + igt_assert_neq(offset, offset2); + gem_close(fd2, flinked_bo); + gem_close(fd, bo); +} + +static void createbo_and_compare_offsets(uint32_t fd, uint32_t fd2, + uint64_t buf_size, + bool needs_32b, bool needs_32b2) +{ + uint32_t bo, bo2; + uint64_t offset, offset2; + + bo = gem_create(fd, buf_size); + offset = exec_and_get_offset(fd, bo, needs_32b); + gem_sync(fd, bo); + + bo2 = gem_create(fd2, buf_size); + offset2 = exec_and_get_offset(fd2, bo2, needs_32b2); + gem_sync(fd2, bo2); + + if (needs_32b == needs_32b2) + igt_assert_eq(offset, offset2); + else + igt_assert_neq(offset, offset2); + + + /* lower PDPs of each PPGTT are reserved for the objects + * requiring this workaround + */ + if (needs_32b) + igt_assert(is_32b(offset)); + + if (needs_32b2) + igt_assert(is_32b(offset2)); + + gem_close(fd, bo); + gem_close(fd2, bo2); +} + +static void wa_32b_offset_test(void) +{ + uint32_t fd, fd2, gb; + + fd = drm_open_any(); + igt_require(uses_48b_full_ppgtt(fd)); + + intel_require_memory(1, 4*G, CHECK_RAM); + + fd2 = drm_open_any(); + + for (gb = 1; gb < 4; gb++) { + /* same bo test */ + reusebo_and_compare_offsets(fd, gb*G); + + + /* allow full addr range */ + createbo_and_compare_offsets(fd, fd2, gb*G, 0, 0); + + /* limit 32b addr range */ + createbo_and_compare_offsets(fd, fd2, gb*G, 1, 1); + + /* mixed */ + createbo_and_compare_offsets(fd, fd2, gb*G, 0, 1); + createbo_and_compare_offsets(fd, fd2, gb*G, 1, 0); + + /* flink obj */ + flinkbo_and_compare_offsets(fd, fd2, gb*G); + } + + close(fd); + close(fd2); +} + + #define N_CHILD 8 int main(int argc, char **argv) { @@ -302,5 +441,8 @@ int main(int argc, char **argv) igt_subtest("flink-and-close-vma-leak") flink_and_close(); + igt_subtest("wa-32b-offset-test") + wa_32b_offset_test(); + igt_exit(); }