Message ID | 1435316058-13913-1-git-send-email-jani.nikula@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Fri, Jun 26, 2015 at 01:54:18PM +0300, Jani Nikula wrote: > Some 855gm models (at least ThinkPad X40) regressed because of > > commit b0cd324faed23d10d66ba6ade66579c681feef6f > Author: Jani Nikula <jani.nikula@intel.com> > Date: Wed Nov 12 16:25:43 2014 +0200 > > drm/i915: don't save/restore backlight hist ctl registers > > which tried to make our driver more robust by not blindly saving and > restoring registers, but it failed to take into account > > commit 0eb96d6ed38430b72897adde58f5477a6b71757a > Author: Jesse Barnes <jbarnes@virtuousgeek.org> > Date: Wed Oct 14 12:33:41 2009 -0700 > > drm/i915: save/restore BLC histogram control reg across suspend/resume > > Fix the regression by enabling hist ctl on gen2. > > v2: Improved the comment. > > Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net> > References: http://mid.gmane.org/20150623222648.GD12335@acheron > Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers") > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: stable@vger.kernel.org > Acked-by: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_panel.c | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index fa9ccb87eb66..bf7c08b94088 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells { > #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ > > #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) > +#define BLM_HISTOGRAM_ENABLE (1 << 31) > > /* New registers for PCH-split platforms. Safe where new bits show up, the > * register layout machtes with gen4 BLC_PWM_CTL[12]. */ > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index 7d83527f95f7..a55477c59559 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector) > > /* XXX: combine this into above write? */ > intel_panel_actually_set_backlight(connector, panel->backlight.level); > + > + /* > + * Needed to enable backlight on some 855gm models. * BLC_HIST_CTL is 855gm only, but checking for gen2 is > + * safe, as 855gm is the only gen2 that has backlight. > + */ I just felt the second sentence lacked a little context to justify itself. -Chris
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6611
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 302/302 302/302
SNB 312/316 312/316
IVB 343/343 343/343
BYT 287/287 287/287
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa9ccb87eb66..bf7c08b94088 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells { #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) +#define BLM_HISTOGRAM_ENABLE (1 << 31) /* New registers for PCH-split platforms. Safe where new bits show up, the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 7d83527f95f7..a55477c59559 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector) /* XXX: combine this into above write? */ intel_panel_actually_set_backlight(connector, panel->backlight.level); + + /* + * Needed to enable backlight on some 855gm models. Checking for gen2 is + * safe, as 855gm is the only gen2 that has backlight. + */ + if (IS_GEN2(dev)) + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } static void i965_enable_backlight(struct intel_connector *connector)