| Message ID | 1435942421-28243-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote: > This patch only enables support for Gen9, the actual WA will be > initialized in subsequent patches. > > The WARN that we use to warn user if WA batch support is not available > for a particular Gen is replaced with DRM_ERROR as warning here doesn't > really add much value. > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++++++--- > 1 file changed, 38 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 23ff018..927f395 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1269,6 +1269,26 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring, > return wa_ctx_end(wa_ctx, *offset = index, 1); > } > > +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, > + struct i915_wa_ctx_bb *wa_ctx, > + uint32_t *const batch, > + uint32_t *offset) > +{ > + /* FIXME: Replace me with WA */ Do the same int index = wa_ctx_begin(); wa_ctx_emit(MI_BATCH_BUFFER_END) (and MI_NOOP for perctx) return wa_ctx_end() you did for gen8. That way the series doesn't suddenly break halfway through (or just after the first patch) and we can check the infrastructure in situ, and the actual wa separately later. -Chris
On 03/07/2015 17:57, Chris Wilson wrote: > On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote: >> This patch only enables support for Gen9, the actual WA will be >> initialized in subsequent patches. >> >> The WARN that we use to warn user if WA batch support is not available >> for a particular Gen is replaced with DRM_ERROR as warning here doesn't >> really add much value. >> >> Cc: Imre Deak <imre.deak@intel.com> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> >> --- >> drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++++++--- >> 1 file changed, 38 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >> index 23ff018..927f395 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1269,6 +1269,26 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring, >> return wa_ctx_end(wa_ctx, *offset = index, 1); >> } >> >> +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, >> + struct i915_wa_ctx_bb *wa_ctx, >> + uint32_t *const batch, >> + uint32_t *offset) >> +{ >> + /* FIXME: Replace me with WA */ > > Do the same int index = wa_ctx_begin(); > > wa_ctx_emit(MI_BATCH_BUFFER_END) (and MI_NOOP for perctx) > > return wa_ctx_end() > > you did for gen8. That way the series doesn't suddenly break halfway > through (or just after the first patch) and we can check the > infrastructure in situ, and the actual wa separately later. (forgot to reply-all) right, will update it along with other review comments, thanks. regards Arun > -Chris >
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 23ff018..927f395 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1269,6 +1269,26 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring, return wa_ctx_end(wa_ctx, *offset = index, 1); } +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, + struct i915_wa_ctx_bb *wa_ctx, + uint32_t *const batch, + uint32_t *offset) +{ + /* FIXME: Replace me with WA */ + DRM_ERROR("No WA available to init in indirect ctx batch buffer"); + return -EINVAL; +} + +static int gen9_init_perctx_bb(struct intel_engine_cs *ring, + struct i915_wa_ctx_bb *wa_ctx, + uint32_t *const batch, + uint32_t *offset) +{ + /* FIXME: Replace me with WA */ + DRM_ERROR("No WA available to init in per ctx batch buffer"); + return -EINVAL; +} + static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) { int ret; @@ -1310,10 +1330,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring) WARN_ON(ring->id != RCS); /* update this when WA for higher Gen are added */ - if (WARN(INTEL_INFO(ring->dev)->gen > 8, - "WA batch buffer is not initialized for Gen%d\n", - INTEL_INFO(ring->dev)->gen)) + if (INTEL_INFO(ring->dev)->gen > 9) { + DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", + INTEL_INFO(ring->dev)->gen); return 0; + } /* some WA perform writes to scratch page, ensure it is valid */ if (ring->scratch.obj == NULL) { @@ -1345,6 +1366,20 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring) &offset); if (ret) goto out; + } else if (INTEL_INFO(ring->dev)->gen == 9) { + ret = gen9_init_indirectctx_bb(ring, + &wa_ctx->indirect_ctx, + batch, + &offset); + if (ret) + goto out; + + ret = gen9_init_perctx_bb(ring, + &wa_ctx->per_ctx, + batch, + &offset); + if (ret) + goto out; } out:
This patch only enables support for Gen9, the actual WA will be initialized in subsequent patches. The WARN that we use to warn user if WA batch support is not available for a particular Gen is replaced with DRM_ERROR as warning here doesn't really add much value. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-)