From patchwork Mon Jul 6 12:42:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 6723511 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5F1079F38C for ; Mon, 6 Jul 2015 12:39:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7CD2F2062F for ; Mon, 6 Jul 2015 12:39:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8DBDA2062C for ; Mon, 6 Jul 2015 12:39:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 125606E881; Mon, 6 Jul 2015 05:39:21 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C5FE6E881 for ; Mon, 6 Jul 2015 05:39:19 -0700 (PDT) Received: by wifm2 with SMTP id m2so28479088wif.1 for ; Mon, 06 Jul 2015 05:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id; bh=rHoN8oJ3A0VvRfLYEC1TUVEgm0EJG9QmiQ7bYKHWemY=; b=C4BBNq/autUPyHEwwHrN7n2rRHcpxIVmyCM/8XI79Hx9Mjggarc0/fyIP5vb7R5heO bimngG1vt4Lz8OmqGmjxUJ4ZQ2wjpA8Nl89/8K/O1wYD276fUtsR04tXjieClXKKClWj CZIC+l20e67SrGlFptr3gF445TJnWcn8cAQ3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rHoN8oJ3A0VvRfLYEC1TUVEgm0EJG9QmiQ7bYKHWemY=; b=hNo1IlUcFOS+8sK4kb/83hml171Epg6ta5z0sPVuBqErMos5KxxCCGgzJl/BCBwPj1 6Rbrvs8rfZEuHnXIg9i+JUXSiR7qhUCTPgSsLAb6ugssz5aPh/Cxnov4m5KaG5wfJet/ Sd5ToX+TYIZ/vhzdoec/C+RDhQ0xZkc0HQVK6DYCEEydEIfB3HZJYj4+1AGQQvNC5kN4 efVCHTJcbBKUc7IcSVzQ2z6kMI8nlOEd01uR7C1GpdJsP0NxGa3Y5BzBaXGa6GAXgQAL B0JVyR7GQoJC82OxgExA1BMB5sWs1uN+e3S2w7mGKVgunu5F/ByORusO5LjvJ9dzRF3Y aTkQ== X-Gm-Message-State: ALoCoQms/U30CTICHystjQPieEZOCo5dupIdctZS53XuaoHc0HDv9lB0uUca0bf/K2WzBX/1SWaD X-Received: by 10.180.91.166 with SMTP id cf6mr51377105wib.61.1436186358214; Mon, 06 Jul 2015 05:39:18 -0700 (PDT) Received: from phenom.ffwll.local (212-51-149-109.fiber7.init7.net. [212.51.149.109]) by mx.google.com with ESMTPSA id fi6sm28403732wib.6.2015.07.06.05.39.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jul 2015 05:39:17 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 6 Jul 2015 14:42:02 +0200 Message-Id: <1436186522-7834-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.1.4 Cc: Daniel Vetter , Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: RMW register cycles considered evil X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Especially for workarounds which is stuff that's almost impossible to verify: The initial state from the firmware on boot-up and after resume could be different, which will hide bugs when we do an RMW cycle. Hence never do them, and if it's required we need a special mask. Cc: Damien Lespiau Cc: Imre Deak Cc: Nick Hoath Signed-off-by: Daniel Vetter Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_pm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 166ae51f5a5b..565f78d6a21d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -57,7 +57,7 @@ static void gen9_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* WaEnableLbsSlaRetryTimerDecrement:skl */ - I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | + I915_WRITE(BDW_SCRATCH1, GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); } @@ -72,18 +72,18 @@ static void skl_init_clock_gating(struct drm_device *dev) * WaDisableSDEUnitClockGating:skl * WaSetGAPSunitClckGateDisable:skl */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | + I915_WRITE(GEN8_UCGCTL6, GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* WaDisableVFUnitClockGating:skl */ - I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | + I915_WRITE(GEN6_UCGCTL2, GEN6_VFUNIT_CLOCK_GATE_DISABLE); } if (INTEL_REVID(dev) <= SKL_REVID_D0) { /* WaDisableHDCInvalidation:skl */ - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | + I915_WRITE(GAM_ECOCHK, BDW_DISABLE_HDC_INVALIDATION); /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ @@ -93,7 +93,7 @@ static void skl_init_clock_gating(struct drm_device *dev) if (INTEL_REVID(dev) <= SKL_REVID_E0) /* WaDisableLSQCROPERFforOCL:skl */ - I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | + I915_WRITE(GEN8_L3SQCREG4, GEN8_LQSC_RO_PERF_DIS); } @@ -109,12 +109,12 @@ static void bxt_init_clock_gating(struct drm_device *dev) * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. */ /* WaDisableSDEUnitClockGating:bxt */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | + I915_WRITE(GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); /* FIXME: apply on A0 only */ - I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); + I915_WRITE(TILECTL, TILECTL_TLBPF); } static void i915_pineview_get_mem_freq(struct drm_device *dev)