From patchwork Tue Jul 7 18:26:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 6736851 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8A423C05AC for ; Tue, 7 Jul 2015 18:27:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 532C82067A for ; Tue, 7 Jul 2015 18:27:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 059FF205FD for ; Tue, 7 Jul 2015 18:26:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CCBB6EA57; Tue, 7 Jul 2015 11:26:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qk0-f180.google.com (mail-qk0-f180.google.com [209.85.220.180]) by gabe.freedesktop.org (Postfix) with ESMTPS id 030286EA35 for ; Tue, 7 Jul 2015 11:26:57 -0700 (PDT) Received: by qkeo142 with SMTP id o142so146247915qke.1 for ; Tue, 07 Jul 2015 11:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UFwpEgCSR5kZbecS81WWRby7yBa5bkISx+me+gDYOck=; b=ulLQ5mZHDwmaRfR18NgdUEM8wymrrGwHIKupIbPT3lfwlhfqs+KY9t2VN9ksedTDt3 7LSf6ELWItH6nngwWYM0MUb0sop5Zx+42m3LZOVDxa/vjWQbqRC5YtUaAt3buwiv/KK+ 77u7/6/KHSFNUSVGaK/SXfR5FS5oyBeS2GPuNqgYn68Wt47IWC5vQxccYQ3GtgcCkiox /D1lutIa8/3s9iTpRT1r2WWBcXvxDHgc/4E2NLdw21GToWFnhHZ2jiMH7bfSGHjtF8Tv eNuNb1/M1fym6XQ11QYgRFvAVH/ZtzypgNucXoHWDYeNyiOyUxhzsZA206O4SN8e+FMm ZEWA== X-Received: by 10.140.39.49 with SMTP id u46mr9143902qgu.5.1436293616200; Tue, 07 Jul 2015 11:26:56 -0700 (PDT) Received: from localhost.localdomain (r130-pw-tresbarras.ibys.com.br. [189.76.1.243]) by mx.google.com with ESMTPSA id h81sm11588457qkh.34.2015.07.07.11.26.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jul 2015 11:26:55 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Jul 2015 15:26:05 -0300 Message-Id: <1436293568-1674-4-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436293568-1674-1-git-send-email-przanoni@gmail.com> References: <1436293568-1674-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/6] drm/i915: use intel_crtc for the FBC functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni This is all internal i915.ko work, let's start using intel_crtc for everything. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/intel_fbc.c | 79 +++++++++++++++++++--------------------- 2 files changed, 40 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7f75ff3..4ef1764 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -918,7 +918,7 @@ struct i915_fbc { struct intel_fbc_work { struct delayed_work work; - struct drm_crtc *crtc; + struct intel_crtc *crtc; struct drm_framebuffer *fb; } *fbc_work; @@ -938,7 +938,7 @@ struct i915_fbc { } no_fbc_reason; bool (*fbc_enabled)(struct drm_i915_private *dev_priv); - void (*enable_fbc)(struct drm_crtc *crtc); + void (*enable_fbc)(struct intel_crtc *crtc); void (*disable_fbc)(struct drm_i915_private *dev_priv); }; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 449dbe4..9ef5b6c 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -64,12 +64,11 @@ static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("disabled FBC\n"); } -static void i8xx_fbc_enable(struct drm_crtc *crtc) +static void i8xx_fbc_enable(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = crtc->dev->dev_private; - struct drm_framebuffer *fb = crtc->primary->fb; + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + struct drm_framebuffer *fb = crtc->base.primary->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int cfb_pitch; int i; u32 fbc_ctl; @@ -96,9 +95,9 @@ static void i8xx_fbc_enable(struct drm_crtc *crtc) /* Set it up... */ fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; - fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); + fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); I915_WRITE(FBC_CONTROL2, fbc_ctl2); - I915_WRITE(FBC_FENCE_OFF, crtc->y); + I915_WRITE(FBC_FENCE_OFF, crtc->base.y); } /* enable it... */ @@ -112,7 +111,7 @@ static void i8xx_fbc_enable(struct drm_crtc *crtc) I915_WRITE(FBC_CONTROL, fbc_ctl); DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", - cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); + cfb_pitch, crtc->base.y, plane_name(crtc->plane)); } static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) @@ -120,29 +119,28 @@ static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) return I915_READ(FBC_CONTROL) & FBC_CTL_EN; } -static void g4x_fbc_enable(struct drm_crtc *crtc) +static void g4x_fbc_enable(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = crtc->dev->dev_private; - struct drm_framebuffer *fb = crtc->primary->fb; + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + struct drm_framebuffer *fb = crtc->base.primary->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); u32 dpfc_ctl; dev_priv->fbc.enabled = true; - dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; + dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) dpfc_ctl |= DPFC_CTL_LIMIT_2X; else dpfc_ctl |= DPFC_CTL_LIMIT_1X; dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; - I915_WRITE(DPFC_FENCE_YOFF, crtc->y); + I915_WRITE(DPFC_FENCE_YOFF, crtc->base.y); /* enable it... */ I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); - DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); + DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); } static void g4x_fbc_disable(struct drm_i915_private *dev_priv) @@ -172,18 +170,17 @@ static void intel_fbc_nuke(struct drm_i915_private *dev_priv) POSTING_READ(MSG_FBC_REND_STATE); } -static void ilk_fbc_enable(struct drm_crtc *crtc) +static void ilk_fbc_enable(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = crtc->dev->dev_private; - struct drm_framebuffer *fb = crtc->primary->fb; + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + struct drm_framebuffer *fb = crtc->base.primary->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; dev_priv->fbc.enabled = true; - dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); + dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) threshold++; @@ -203,7 +200,7 @@ static void ilk_fbc_enable(struct drm_crtc *crtc) if (IS_GEN5(dev_priv)) dpfc_ctl |= obj->fence_reg; - I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); + I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->base.y); I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); /* enable it... */ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); @@ -211,12 +208,12 @@ static void ilk_fbc_enable(struct drm_crtc *crtc) if (IS_GEN6(dev_priv)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); } intel_fbc_nuke(dev_priv); - DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); + DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); } static void ilk_fbc_disable(struct drm_i915_private *dev_priv) @@ -240,12 +237,11 @@ static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; } -static void gen7_fbc_enable(struct drm_crtc *crtc) +static void gen7_fbc_enable(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = crtc->dev->dev_private; - struct drm_framebuffer *fb = crtc->primary->fb; + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + struct drm_framebuffer *fb = crtc->base.primary->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; @@ -253,7 +249,7 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) - dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane); + dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) threshold++; @@ -285,18 +281,18 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) ILK_FBCQ_DIS); } else { /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), - I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | + I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), + I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | HSW_FBCQ_DIS); } I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); intel_fbc_nuke(dev_priv); - DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); + DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); } /** @@ -317,19 +313,20 @@ static void intel_fbc_work_fn(struct work_struct *__work) struct intel_fbc_work *work = container_of(to_delayed_work(__work), struct intel_fbc_work, work); - struct drm_i915_private *dev_priv = work->crtc->dev->dev_private; + struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; + struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; mutex_lock(&dev_priv->fbc.lock); if (work == dev_priv->fbc.fbc_work) { /* Double check that we haven't switched fb without cancelling * the prior work. */ - if (work->crtc->primary->fb == work->fb) { + if (crtc_fb == work->fb) { dev_priv->fbc.enable_fbc(work->crtc); - dev_priv->fbc.crtc = to_intel_crtc(work->crtc); - dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; - dev_priv->fbc.y = work->crtc->y; + dev_priv->fbc.crtc = work->crtc; + dev_priv->fbc.fb_id = crtc_fb->base.id; + dev_priv->fbc.y = work->crtc->base.y; } dev_priv->fbc.fbc_work = NULL; @@ -364,10 +361,10 @@ static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) dev_priv->fbc.fbc_work = NULL; } -static void intel_fbc_enable(struct drm_crtc *crtc) +static void intel_fbc_enable(struct intel_crtc *crtc) { struct intel_fbc_work *work; - struct drm_i915_private *dev_priv = crtc->dev->dev_private; + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); @@ -381,7 +378,7 @@ static void intel_fbc_enable(struct drm_crtc *crtc) } work->crtc = crtc; - work->fb = crtc->primary->fb; + work->fb = crtc->base.primary->fb; INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); dev_priv->fbc.fbc_work = work; @@ -805,7 +802,7 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv) __intel_fbc_disable(dev_priv); } - intel_fbc_enable(crtc); + intel_fbc_enable(intel_crtc); dev_priv->fbc.no_fbc_reason = FBC_OK; return; @@ -852,7 +849,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv, fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); else if (dev_priv->fbc.fbc_work) fbc_bits = INTEL_FRONTBUFFER_PRIMARY( - to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe); + dev_priv->fbc.fbc_work->crtc->pipe); else fbc_bits = dev_priv->fbc.possible_framebuffer_bits;