From patchwork Wed Jul 8 20:58:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 6751441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6867FC05AD for ; Wed, 8 Jul 2015 20:59:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8E22820661 for ; Wed, 8 Jul 2015 20:59:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AEE5920647 for ; Wed, 8 Jul 2015 20:59:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 386096EBE9; Wed, 8 Jul 2015 13:59:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qk0-f180.google.com (mail-qk0-f180.google.com [209.85.220.180]) by gabe.freedesktop.org (Postfix) with ESMTPS id 32E1B6EBE5 for ; Wed, 8 Jul 2015 13:59:45 -0700 (PDT) Received: by qkeo142 with SMTP id o142so172719114qke.1 for ; Wed, 08 Jul 2015 13:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V1dE0ZxXci9x2sDd3J1du/CmS0J958hpVv8ju10kI6k=; b=cx50Gw85qOzjQEYRZMwOD+V0JAtJJyaU6QnvmAcD2BTVhxZZi75Jf9A9z60uR2q00b IVOAPIthsfkV3CU7G9c6/0iyn0oe82tSvBAbypeqjBLiAhsT9JH2CZoMesLbL6TAvnb2 UudoiUxuoBvTCGZmA9VPhMBdtVVz5skcpddsG8kns4PwwK/09pvXd/YwZKFx/rNTIL+R wf4AMuXNjEEsqxMU5CVZM6brQxiPv4rjez2JTLbeuEMaKH5AkF5ojitwXzSVtG0ma2h9 rhN6F038qEIcNUoSqooMVh/GSO7cU0eAZ6y44OXs5uyVWmXwSRZY4xg0syVSMIrcgrrN lk5A== X-Received: by 10.55.16.146 with SMTP id 18mr13811652qkq.53.1436389184503; Wed, 08 Jul 2015 13:59:44 -0700 (PDT) Received: from localhost.localdomain (r130-pw-tresbarras.ibys.com.br. [189.76.1.243]) by smtp.gmail.com with ESMTPSA id n62sm2099461qha.18.2015.07.08.13.59.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Jul 2015 13:59:43 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Jul 2015 17:58:57 -0300 Message-Id: <1436389139-16282-5-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436389139-16282-1-git-send-email-przanoni@gmail.com> References: <1436389139-16282-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 4/6] drm/i915: set ILK_DPFC_FENCE_YOFF to 0 on SNB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni The doc is pretty clear that this register should be set to 0 on SNB. We already write y_offset to DPFC_CPU_FENCE_OFFSET a few lines below. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 0373cbc..0a24e96 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -216,7 +216,12 @@ static void ilk_fbc_enable(struct intel_crtc *crtc) dpfc_ctl |= obj->fence_reg; y_offset = get_crtc_fence_y_offset(crtc); - I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); + + if (IS_GEN5(dev_priv)) + I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); + else + I915_WRITE(ILK_DPFC_FENCE_YOFF, 0); + I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); /* enable it... */ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);