From patchwork Thu Jul 9 19:29:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 6758531 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D50959F380 for ; Thu, 9 Jul 2015 19:30:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E1797206FC for ; Thu, 9 Jul 2015 19:30:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 063D1206C0 for ; Thu, 9 Jul 2015 19:30:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E128E6E3C4; Thu, 9 Jul 2015 12:30:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qg0-f42.google.com (mail-qg0-f42.google.com [209.85.192.42]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA2F06E3C4 for ; Thu, 9 Jul 2015 12:30:06 -0700 (PDT) Received: by qgep37 with SMTP id p37so27770656qge.1 for ; Thu, 09 Jul 2015 12:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MkaFiqTgGQTcdSRltanx2BD7ospNymfOw6IX4P46iYE=; b=halEvysOGoOpPSbPPT5DOqFaMVkY8R3cTfCm7Xrp3Hg4hjCsuJu3Ic+3BKjVE93WM5 YUnT/OOadoXlqmkv8RNVGJIVemOk1wrIerBB4ohVZaT+qL5V54dE5gic6TIVfuJjuBsW vy1C62ap7XD4Rj0uNcHTa+5QOAeukkt+OHJc/tic+4JJEce2I7v4UDm8qw7fxXT2EpLl W+KChG+/ug8B1Qf1ASF43oXB3OBfgtaCkTerTV+XX2l0L2WcH6e/NSAQvmzOGg5wt6oW L3+4iyfGxSR1vnsiy+DLNk2T7OnSWldCHBLkAbiAlJqRM19czUU1XaQE3IpEH/cvRldK 1RpQ== X-Received: by 10.140.202.84 with SMTP id x81mr24180417qha.50.1436470205972; Thu, 09 Jul 2015 12:30:05 -0700 (PDT) Received: from localhost.localdomain (r130-pw-tresbarras.ibys.com.br. [189.76.1.243]) by smtp.gmail.com with ESMTPSA id p26sm3903833qkp.11.2015.07.09.12.30.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jul 2015 12:30:05 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Jul 2015 16:29:24 -0300 Message-Id: <1436470164-6873-1-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 5/6] drm/i915: check for the supported strides on HSW+ FBC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni I could only find the restrictions for HSW+, but I think it's safe to assume that the older platforms also can't support the configurations HSW can't support. The older platforms probably have additional restrictions, so we need to figure out those and implement them later. Let's not block HSW+ FBC based on missing information for the older platforms. v2 - Just WARN_ON() the strides that should have been caught earlier (Daniel) - Make it a new function since I expect this to grow more. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_fbc.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 768d1db..6cde34f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -937,6 +937,7 @@ struct i915_fbc { FBC_CHIP_DEFAULT, /* disabled by default on this chip */ FBC_ROTATION, /* rotation is not supported */ FBC_IN_DBG_MASTER, /* kernel debugger is active */ + FBC_BAD_STRIDE, /* stride is not supported */ } no_fbc_reason; bool (*fbc_enabled)(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 0a24e96..f221c0e 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -501,6 +501,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) return "rotation unsupported"; case FBC_IN_DBG_MASTER: return "Kernel debugger is active"; + case FBC_BAD_STRIDE: + return "framebuffer stride not supported"; default: MISSING_CASE(reason); return "unknown reason"; @@ -694,6 +696,22 @@ static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size, return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp); } +static bool stride_is_valid(unsigned int stride) +{ + /* TODO: we need to figure out what are the stride restrictions for the + * older platforms. */ + + /* These should have been caught earlier. */ + WARN_ON(stride < 512); + WARN_ON((stride & (64 - 1)) != 0); + + /* These are additional FBC restrictions. */ + if (stride > 16385) + return false; + + return true; +} + /** * __intel_fbc_update - enable/disable FBC as needed, unlocked * @dev_priv: i915 device instance @@ -804,6 +822,11 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv) goto out_disable; } + if (!stride_is_valid(fb->pitches[0])) { + set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); + goto out_disable; + } + /* If the kernel debugger is active, always disable compression */ if (in_dbg_master()) { set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER);