From patchwork Thu Jul 9 20:04:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 6758561 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6A568C05AC for ; Thu, 9 Jul 2015 20:02:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8256F206F7 for ; Thu, 9 Jul 2015 20:02:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 96D26206C0 for ; Thu, 9 Jul 2015 20:02:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D38C6ED2E; Thu, 9 Jul 2015 13:02:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D8C26ED2E for ; Thu, 9 Jul 2015 13:02:12 -0700 (PDT) Received: by wicmv11 with SMTP id mv11so9525311wic.1 for ; Thu, 09 Jul 2015 13:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0hFJOXX8M48uQFgwsiKP2FLvg4flSaG7PdZBqo8rg/M=; b=NU2+fEpIfGvq5clvOP4EA3bOpSVrvskfgVh4EZMLygMnxaUdCrt14sYy3x5iLPXPMt DCubi27ghnBqZRJnbhETdOTN2fxE7ssf5kfCgnW2JHpax0KcM/tnfbFjL5jxF74pGR4k jX16ekpUXxMk2qVZWMGHe9HPhqAKKM6rqANUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0hFJOXX8M48uQFgwsiKP2FLvg4flSaG7PdZBqo8rg/M=; b=Zo93o2HyCRbQegGJVsgVEXRSRgqJdt8P6xTbRROHtwNp7Pi1pMXj/IMvOhBrRhYUKU BLnWWhK0vkPE1J/3u7XIoNASY319QJTuRXJ1PE1dAmxN7GwLIxfJ8Ld8CME1uROjGDUz HRjGRHENTbqmyopqospJeb5Rx1n9aFwcOtvmjjRb1kOj0R1WWwIaUuloXcOm+fodgvRc 3N0Y/oXcKUaOoRpoY9S4BDwQXeWhGRAEoP0TDj2cceQ2SNkE08dCHb7OXqA2FJx7wFuK skTbCnlSOzN752iYxd38g7D9HpeLG/G3/dbX5akeVuhOFlHZWPjR3I7mrcljH8F8HvaY GFzA== X-Gm-Message-State: ALoCoQlhK/4UaNHnHHgRCInBp3s2iZZ/0APTfENngARKGiIl5UA4NspnUy/xp61dGv6C6ynvY+73 X-Received: by 10.194.104.98 with SMTP id gd2mr31575925wjb.35.1436472130557; Thu, 09 Jul 2015 13:02:10 -0700 (PDT) Received: from phenom.ffwll.local (212-51-149-109.fiber7.init7.net. [212.51.149.109]) by smtp.gmail.com with ESMTPSA id i5sm9807972wic.10.2015.07.09.13.02.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jul 2015 13:02:08 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 9 Jul 2015 22:04:38 +0200 Message-Id: <1436472288-595-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436472288-595-1-git-send-email-daniel.vetter@ffwll.ch> References: <1436365487-19242-1-git-send-email-animesh.manna@intel.com> <1436472288-595-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter , Daniel Vetter Subject: [Intel-gfx] [PATCH 02/12] drm/i915: Only allow rpm on gen9+ with dmc loaded X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of trying to deal with this complexity we'll simply require that the dmc firmware is available for runtime pm support. We do that by not releasing the rpm reference we acquire when starting the firmware loader work. Note that since we hold a rpm reference (and rpm get/put is synchronized with its own locking already) there's no need for any additional synchronization between the dmc loader and the rpm entry/exit code. Hence we can remove all dmc_load_status_get calls, they don't do anything any more. Cc: Animesh Manna Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_csr.c | 9 +++++---- drivers/gpu/drm/i915/intel_runtime_pm.c | 17 +++-------------- 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 16cd9dae1c1b..03d83892cdb0 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -393,8 +393,11 @@ static void finish_csr_load(const struct firmware *fw, void *context) out: if (fw_loaded) intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); - else - intel_csr_load_status_set(dev_priv, FW_FAILED); + + /* + * We require the dmc firmware for runtime pm on gen9+ - leak the rpm + * reference in case this failed to disable rpm on. + */ release_firmware(fw); } @@ -462,8 +465,6 @@ void intel_csr_ucode_fini(struct drm_device *dev) void assert_csr_loaded(struct drm_i915_private *dev_priv) { - WARN(intel_csr_load_status_get(dev_priv) != FW_LOADED, - "CSR is not loaded.\n"); WARN(!I915_READ(CSR_PROGRAM_BASE), "CSR program storage start is NULL\n"); WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 2628b21ff2c0..ed8c0cee738f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -644,21 +644,10 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && power_well->data == SKL_DISP_PW_2) { - enum csr_state state; - /* TODO: wait for a completion event or - * similar here instead of busy - * waiting using wait_for function. - */ - wait_for((state = intel_csr_load_status_get(dev_priv)) != - FW_UNINITIALIZED, 1000); - if (state != FW_LOADED) - DRM_ERROR("CSR firmware not ready (%d)\n", - state); + if (SKL_ENABLE_DC6(dev)) + skl_enable_dc6(dev_priv); else - if (SKL_ENABLE_DC6(dev)) - skl_enable_dc6(dev_priv); - else - gen9_enable_dc5(dev_priv); + gen9_enable_dc5(dev_priv); } } }