| Message ID | 1436881275-15459-1-git-send-email-nicholas.hoath@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Nick Hoath <nicholas.hoath@intel.com> writes: > v2: Patch leakage fixed > > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 059de0f..afa8972 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -160,6 +160,7 @@ > #define GAM_ECOCHK 0x4090 > #define BDW_DISABLE_HDC_INVALIDATION (1<<25) > #define ECOCHK_SNB_BIT (1<<10) > +#define ECOCHK_DIS_TLB (1<<8) > #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) > #define ECOCHK_PPGTT_CACHE64B (0x3<<3) > #define ECOCHK_PPGTT_CACHE4B (0x0<<3) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index f2be1ce..6986342 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -59,6 +59,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) > /* WaEnableLbsSlaRetryTimerDecrement:skl */ > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > + > + /* WaDisableKillLogic:bxt,skl */ > + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > + ECOCHK_DIS_TLB); > } > > static void skl_init_clock_gating(struct drm_device *dev) > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Jul 15, 2015 at 01:51:05PM +0300, Mika Kuoppala wrote: > Nick Hoath <nicholas.hoath@intel.com> writes: > > > v2: Patch leakage fixed > > > > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Queued for -next, thanks for the patch. -Daniel > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > > 3 files changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 059de0f..afa8972 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -160,6 +160,7 @@ > > #define GAM_ECOCHK 0x4090 > > #define BDW_DISABLE_HDC_INVALIDATION (1<<25) > > #define ECOCHK_SNB_BIT (1<<10) > > +#define ECOCHK_DIS_TLB (1<<8) > > #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) > > #define ECOCHK_PPGTT_CACHE64B (0x3<<3) > > #define ECOCHK_PPGTT_CACHE4B (0x0<<3) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index f2be1ce..6986342 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -59,6 +59,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) > > /* WaEnableLbsSlaRetryTimerDecrement:skl */ > > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > + > > + /* WaDisableKillLogic:bxt,skl */ > > + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > > + ECOCHK_DIS_TLB); > > } > > > > static void skl_init_clock_gating(struct drm_device *dev) > > -- > > 2.1.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 059de0f..afa8972 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -160,6 +160,7 @@ #define GAM_ECOCHK 0x4090 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) #define ECOCHK_SNB_BIT (1<<10) +#define ECOCHK_DIS_TLB (1<<8) #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) #define ECOCHK_PPGTT_CACHE64B (0x3<<3) #define ECOCHK_PPGTT_CACHE4B (0x0<<3) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f2be1ce..6986342 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -59,6 +59,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) /* WaEnableLbsSlaRetryTimerDecrement:skl */ I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); + + /* WaDisableKillLogic:bxt,skl */ + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | + ECOCHK_DIS_TLB); } static void skl_init_clock_gating(struct drm_device *dev)
v2: Patch leakage fixed Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-)