From patchwork Sat Jul 25 19:00:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 6865421 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DB38FC05AC for ; Sat, 25 Jul 2015 19:01:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5D6020615 for ; Sat, 25 Jul 2015 19:00:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B3FF620611 for ; Sat, 25 Jul 2015 19:00:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06D3C6E4C6; Sat, 25 Jul 2015 12:00:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 61E9E6E4C6 for ; Sat, 25 Jul 2015 12:00:57 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 25 Jul 2015 12:00:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,543,1432623600"; d="scan'208";a="735456114" Received: from amanna-desktop.iind.intel.com ([10.223.25.39]) by orsmga001.jf.intel.com with ESMTP; 25 Jul 2015 12:00:55 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Sun, 26 Jul 2015 00:30:31 +0530 Message-Id: <1437850839-16782-11-git-send-email-animesh.manna@intel.com> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1437850839-16782-1-git-send-email-animesh.manna@intel.com> References: <1437850839-16782-1-git-send-email-animesh.manna@intel.com> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 10/18] drm/i915/gen9: extract parse_csr_fw. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Vetter The loader function will get a bit more complicated soon, extract the parsing code to make the control flow clearer. While doing that just use dev_priv->csr.dmc_payload as the indicator for whether it all suceeded or not. Also restrict the forced big-edian casting to just one place. Cc: Damien Lespiau Cc: Imre Deak Cc: Sunil Kamath Signed-off-by: Daniel Vetter Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/intel_csr.c | 58 +++++++++++++++++++-------------- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 381d891..0813ff2 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -207,7 +207,7 @@ static char intel_get_substepping(struct drm_device *dev) void intel_csr_load_program(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - __be32 *payload = dev_priv->csr.dmc_payload; + uint32_t *payload = dev_priv->csr.dmc_payload; uint32_t i, fw_size; if (!IS_GEN9(dev)) { @@ -217,8 +217,7 @@ void intel_csr_load_program(struct drm_device *dev) fw_size = dev_priv->csr.dmc_fw_size; for (i = 0; i < fw_size; i++) - I915_WRITE(CSR_PROGRAM_BASE + i * 4, - (u32 __force)payload[i]); + I915_WRITE(CSR_PROGRAM_BASE + i * 4, payload[i]); for (i = 0; i < dev_priv->csr.mmio_count; i++) { I915_WRITE(dev_priv->csr.mmioaddr[i], @@ -226,9 +225,9 @@ void intel_csr_load_program(struct drm_device *dev) } } -static void finish_csr_load(const struct firmware *fw, void *context) +static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, + const struct firmware *fw) { - struct drm_i915_private *dev_priv = context; struct drm_device *dev = dev_priv->dev; struct intel_css_header *css_header; struct intel_package_header *package_header; @@ -238,15 +237,11 @@ static void finish_csr_load(const struct firmware *fw, void *context) char substepping = intel_get_substepping(dev); uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; uint32_t i; - __be32 *dmc_payload; - bool fw_loaded = false; - - if (!fw) - goto out; + uint32_t *dmc_payload; if ((stepping == -ENODATA) || (substepping == -ENODATA)) { DRM_ERROR("Unknown stepping info, firmware loading failed\n"); - goto out; + return NULL; } /* Extract CSS Header information*/ @@ -255,7 +250,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) (css_header->header_len * 4)) { DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", (css_header->header_len * 4)); - goto out; + return NULL; } readcount += sizeof(struct intel_css_header); @@ -266,7 +261,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) (package_header->header_len * 4)) { DRM_ERROR("Firmware has wrong package header length %u bytes\n", (package_header->header_len * 4)); - goto out; + return NULL; } readcount += sizeof(struct intel_package_header); @@ -286,7 +281,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) } if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { DRM_ERROR("Firmware not supported for %c stepping\n", stepping); - goto out; + return NULL; } readcount += dmc_offset; @@ -295,7 +290,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", (dmc_header->header_len)); - goto out; + return NULL; } readcount += sizeof(struct intel_dmc_header); @@ -303,7 +298,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { DRM_ERROR("Firmware has wrong mmio count %u\n", dmc_header->mmio_count); - goto out; + return NULL; } csr->mmio_count = dmc_header->mmio_count; for (i = 0; i < dmc_header->mmio_count; i++) { @@ -311,7 +306,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", dmc_header->mmioaddr[i]); - goto out; + return NULL; } csr->mmioaddr[i] = dmc_header->mmioaddr[i]; csr->mmiodata[i] = dmc_header->mmiodata[i]; @@ -321,17 +316,16 @@ static void finish_csr_load(const struct firmware *fw, void *context) nbytes = dmc_header->fw_size * 4; if (nbytes > CSR_MAX_FW_SIZE) { DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); - goto out; + return NULL; } csr->dmc_fw_size = dmc_header->fw_size; - csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL); - if (!csr->dmc_payload) { + dmc_payload = kmalloc(nbytes, GFP_KERNEL); + if (!dmc_payload) { DRM_ERROR("Memory allocation failed for dmc payload\n"); - goto out; + return NULL; } - dmc_payload = csr->dmc_payload; for (i = 0; i < dmc_header->fw_size; i++) { uint32_t *tmp = (u32 *)&fw->data[readcount + i * 4]; /* @@ -339,16 +333,30 @@ static void finish_csr_load(const struct firmware *fw, void *context) * little-endian format in the firmware image and programmed * as 32 bit big-endian format to memory. */ - dmc_payload[i] = cpu_to_be32(*tmp); + dmc_payload[i] = (uint32_t __force) cpu_to_be32(*tmp); } + return dmc_payload; +} + +static void finish_csr_load(const struct firmware *fw, void *context) +{ + struct drm_i915_private *dev_priv = context; + struct drm_device *dev = dev_priv->dev; + + if (!fw) + goto out; + + dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); + if (!dev_priv->csr.dmc_payload) + goto out; + /* load csr program during system boot, as needed for DC states */ intel_csr_load_program(dev); - fw_loaded = true; DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path); out: - if (fw_loaded || IS_BROXTON(dev)) + if (dev_priv->csr.dmc_payload || IS_BROXTON(dev)) intel_runtime_pm_put(dev_priv); else DRM_ERROR("Failed to load DMC firmware, disabling rpm\n"); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1067aa2..5f1ae23 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1139,7 +1139,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { WARN_ON(!power_well->count); if (IS_SKYLAKE(dev_priv) && (power_well->data == SKL_DISP_PW_1) && - (intel_csr_load_status_get(dev_priv) == FW_LOADED)) + dev_priv->csr.dmc_payload) DRM_DEBUG_KMS("dmc will disable pw1"); else if (!--power_well->count && i915.disable_power_well) { DRM_DEBUG_KMS("disabling %s\n", power_well->name);