| Message ID | 1438344840-3490-8-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 31, 2015 at 03:13:56PM +0300, Mika Kahola wrote: > It is possible the we request to have a mode that has > higher pixel clock than our HW can support. This patch > checks if requested pixel clock is lower than the one > supported by the HW. The requested mode is discarded > if we cannot support the requested pixel clock. > > This patch applies to CRT. > > V2: > - removed computation for max pixel clock > > V3: > - cleanup by removing unnecessary lines > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_crt.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index 5d78c1f..40ded5f 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -290,6 +290,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > struct drm_display_mode *mode) > { > struct drm_device *dev = connector->dev; > + int max_pixclk = to_i915(dev)->max_dotclk; > > int max_clock = 0; > if (mode->flags & DRM_MODE_FLAG_DBLSCAN) > @@ -305,6 +306,9 @@ intel_crt_mode_valid(struct drm_connector *connector, > if (mode->clock > max_clock) > return MODE_CLOCK_HIGH; > > + if (mode->clock > max_pixclk) > + return MODE_CLOCK_HIGH; > + > /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ > if (HAS_PCH_LPT(dev) && > (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 5d78c1f..40ded5f 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -290,6 +290,7 @@ intel_crt_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { struct drm_device *dev = connector->dev; + int max_pixclk = to_i915(dev)->max_dotclk; int max_clock = 0; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) @@ -305,6 +306,9 @@ intel_crt_mode_valid(struct drm_connector *connector, if (mode->clock > max_clock) return MODE_CLOCK_HIGH; + if (mode->clock > max_pixclk) + return MODE_CLOCK_HIGH; + /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ if (HAS_PCH_LPT(dev) && (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported by the HW. The requested mode is discarded if we cannot support the requested pixel clock. This patch applies to CRT. V2: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_crt.c | 4 ++++ 1 file changed, 4 insertions(+)