From patchwork Mon Aug 3 09:31:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Paneri X-Patchwork-Id: 6928201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 076739F38B for ; Mon, 3 Aug 2015 09:24:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 25314205CB for ; Mon, 3 Aug 2015 09:24:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2FF5A205C4 for ; Mon, 3 Aug 2015 09:24:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5EFC6E4AB; Mon, 3 Aug 2015 02:24:42 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B1AD6E4AB for ; Mon, 3 Aug 2015 02:24:41 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 03 Aug 2015 02:24:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,600,1432623600"; d="scan'208";a="775580012" Received: from intel-desktop.iind.intel.com ([10.223.82.37]) by fmsmga002.fm.intel.com with ESMTP; 03 Aug 2015 02:24:39 -0700 From: Praveen Paneri To: intel-gfx@lists.freedesktop.org Date: Mon, 3 Aug 2015 15:01:01 +0530 Message-Id: <1438594261-2946-1-git-send-email-praveen.paneri@intel.com> X-Mailer: git-send-email 1.9.1 Cc: Deepak S , Praveen Paneri Subject: [Intel-gfx] [PATCH] drm/i915/vlv: Add RPS debugfs disabling for vlv/chv X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch exposes a new debugfs interface 'i915_rps_disable' Following 2 values shall be echoed into this file. '0' - RPS explicitly enabled . '1' - RPS explicitly disabled. This interface provides capabilty to enable/disable Turbo feature at runtime, which is needed for its validation. Signed-off-by: Deepak S Signed-off-by: Praveen Paneri Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_debugfs.c | 55 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 23a69307..9124654 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4771,6 +4771,60 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, i915_min_freq_get, i915_min_freq_set, "%llu\n"); +static int i915_rps_disable_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_VALLEYVIEW(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + *val = dev_priv->rps.rps_disable; + + return 0; +} + +static int i915_rps_disable_set(void *data, u64 val) +{ + struct drm_device *dev = data; + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + if (!IS_VALLEYVIEW(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + DRM_DEBUG_DRIVER("Setting RPS disable %s\n", + val ? "true" : "false"); + + ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); + if (ret) + return ret; + + dev_priv->rps.rps_disable = val; + + if (val) + I915_WRITE(GEN6_RP_CONTROL, 0); + else + I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | + GEN6_RP_MEDIA_HW_NORMAL_MODE | + GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | + GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_CONT); + + mutex_unlock(&dev_priv->rps.hw_lock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rps_disable_fops, + i915_rps_disable_get, i915_rps_disable_set, + "%llu\n"); + static int i915_cache_sharing_get(void *data, u64 *val) { @@ -5107,6 +5161,7 @@ static const struct i915_debugfs_files { {"i915_wedged", &i915_wedged_fops}, {"i915_max_freq", &i915_max_freq_fops}, {"i915_min_freq", &i915_min_freq_fops}, + {"i915_rps_disable", &i915_rps_disable_fops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, {"i915_ring_stop", &i915_ring_stop_fops}, {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 04aa34a..e2a57f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1137,6 +1137,8 @@ struct intel_gen6_power_mgmt { u8 up_threshold; /* Current %busy required to uplock */ u8 down_threshold; /* Current %busy required to downclock */ + bool rps_disable; + int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power;