| Message ID | 1438968817-29286-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote: > This WA doesn't have a name. According to the spec, driver need to reset > disable gather at set shader bit in per ctx WA batch. It is to be noted > that the default value is already '0' for this bit but we still need to > apply this WA because userspace may set it. If userspace really need it > to be set then they need to do in every batch. > > Cc: Ben Widawsky <benjamin.widawsky@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ea46d68..838537f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5834,6 +5834,7 @@ enum skl_disp_power_wells { > # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) > # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) > #define COMMON_SLICE_CHICKEN2 0x7014 > +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12) > # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) > > #define HIZ_CHICKEN 0x7018 > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 4c40614..df3bb98 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, > struct drm_device *dev = ring->dev; > uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); > > + /* WaNoName:skl,bxt > + * This WA has no name, according to the spec driver needs to reset > + * "disable gather at set shader slice" bit in per ctx batch > + */ > + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2); > + wa_ctx_emit(batch, index, > + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE)); > + > /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || > (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { Hmm. I thought we needed this, but looking at the "User Mode Privileged Commands" of the spec, it seems like this register is not allowed to be written. So unless this register is put in a whitelist somewhere in the future, I think it's safe to drop this patch. As a preventative measure, I don't see this as harmful - but I don't feel I have any authority to suggest whether we keep this in or not.
On 08/08/2015 06:35, Ben Widawsky wrote: > On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote: >> This WA doesn't have a name. According to the spec, driver need to reset >> disable gather at set shader bit in per ctx WA batch. It is to be noted >> that the default value is already '0' for this bit but we still need to >> apply this WA because userspace may set it. If userspace really need it >> to be set then they need to do in every batch. >> >> Cc: Ben Widawsky <benjamin.widawsky@intel.com> >> Cc: Mika Kuoppala <mika.kuoppala@intel.com> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++ >> 2 files changed, 10 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index ea46d68..838537f 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -5834,6 +5834,7 @@ enum skl_disp_power_wells { >> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) >> # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) >> #define COMMON_SLICE_CHICKEN2 0x7014 >> +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12) >> # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) >> >> #define HIZ_CHICKEN 0x7018 >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >> index 4c40614..df3bb98 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, >> struct drm_device *dev = ring->dev; >> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); >> >> + /* WaNoName:skl,bxt >> + * This WA has no name, according to the spec driver needs to reset >> + * "disable gather at set shader slice" bit in per ctx batch >> + */ >> + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); >> + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2); >> + wa_ctx_emit(batch, index, >> + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE)); >> + >> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ >> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || >> (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { > > Hmm. I thought we needed this, but looking at the "User Mode Privileged > Commands" of the spec, it seems like this register is not allowed to be written. > So unless this register is put in a whitelist somewhere in the future, I think > it's safe to drop this patch. We need to whitelist few registers for preemption related WA, this can be added to whitelist if userspace really needs to write to it. regards Arun > > As a preventative measure, I don't see this as harmful - but I don't feel I have > any authority to suggest whether we keep this in or not. >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ea46d68..838537f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5834,6 +5834,7 @@ enum skl_disp_power_wells { # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) #define COMMON_SLICE_CHICKEN2 0x7014 +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12) # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) #define HIZ_CHICKEN 0x7018 diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4c40614..df3bb98 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, struct drm_device *dev = ring->dev; uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); + /* WaNoName:skl,bxt + * This WA has no name, according to the spec driver needs to reset + * "disable gather at set shader slice" bit in per ctx batch + */ + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2); + wa_ctx_emit(batch, index, + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE)); + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
This WA doesn't have a name. According to the spec, driver need to reset disable gather at set shader bit in per ctx WA batch. It is to be noted that the default value is already '0' for this bit but we still need to apply this WA because userspace may set it. If userspace really need it to be set then they need to do in every batch. Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++ 2 files changed, 10 insertions(+)