From patchwork Thu Aug 13 14:55:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 7008871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CF44F9F39D for ; Thu, 13 Aug 2015 14:56:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D17692075A for ; Thu, 13 Aug 2015 14:56:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D5EF920760 for ; Thu, 13 Aug 2015 14:56:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D3CC72097; Thu, 13 Aug 2015 07:56:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id E5EB172097 for ; Thu, 13 Aug 2015 07:56:14 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 13 Aug 2015 07:56:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,670,1432623600"; d="scan'208";a="747928072" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.88]) by orsmga001.jf.intel.com with SMTP; 13 Aug 2015 07:56:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Aug 2015 17:55:58 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Aug 2015 17:55:52 +0300 Message-Id: <1439477755-24811-2-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.4.6 In-Reply-To: <1439477755-24811-1-git-send-email-ville.syrjala@linux.intel.com> References: <1439477755-24811-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Clean up SDVO limited color range handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Clean up the limited color range handling for SDVO as was done for HDMI/DP previously. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_sdvo.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index c98098e..33e58c1 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -103,7 +103,7 @@ struct intel_sdvo { * This is used to select the color range of RBG outputs in HDMI mode. * It is only valid when using TMDS encoding and 8 bit per color mode. */ - uint32_t color_range; + bool limited_color_range; bool color_range_auto; /** @@ -1166,15 +1166,12 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, if (intel_sdvo->color_range_auto) { /* See CEA-861-E - 5.1 Default Encoding Parameters */ - /* FIXME: This bit is only valid when using TMDS encoding and 8 - * bit per color mode. */ - if (pipe_config->has_hdmi_sink && - drm_match_cea_mode(adjusted_mode) > 1) - pipe_config->limited_color_range = true; + pipe_config->limited_color_range = + pipe_config->has_hdmi_sink && + drm_match_cea_mode(adjusted_mode) > 1; } else { - if (pipe_config->has_hdmi_sink && - intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) - pipe_config->limited_color_range = true; + pipe_config->limited_color_range = + intel_sdvo->limited_color_range; } /* Clock computation needs to happen after pixel multiplier. */ @@ -1268,6 +1265,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; + /* FIXME: this bit is only valid when using TMDS + * encoding and 8 bit per color mode. */ if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; if (INTEL_INFO(dev)->gen < 5) @@ -2017,7 +2016,7 @@ intel_sdvo_set_property(struct drm_connector *connector, if (property == dev_priv->broadcast_rgb_property) { bool old_auto = intel_sdvo->color_range_auto; - uint32_t old_range = intel_sdvo->color_range; + bool old_range = intel_sdvo->limited_color_range; switch (val) { case INTEL_BROADCAST_RGB_AUTO: @@ -2025,20 +2024,18 @@ intel_sdvo_set_property(struct drm_connector *connector, break; case INTEL_BROADCAST_RGB_FULL: intel_sdvo->color_range_auto = false; - intel_sdvo->color_range = 0; + intel_sdvo->limited_color_range = false; break; case INTEL_BROADCAST_RGB_LIMITED: intel_sdvo->color_range_auto = false; - /* FIXME: this bit is only valid when using TMDS - * encoding and 8 bit per color mode. */ - intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; + intel_sdvo->limited_color_range = true; break; default: return -EINVAL; } if (old_auto == intel_sdvo->color_range_auto && - old_range == intel_sdvo->color_range) + old_range == intel_sdvo->limited_color_range) return 0; goto done;