From patchwork Thu Aug 13 20:31:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 7010931 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3C7549F344 for ; Thu, 13 Aug 2015 20:54:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F07E2067D for ; Thu, 13 Aug 2015 20:54:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E3F162064D for ; Thu, 13 Aug 2015 20:54:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 708406E5CB; Thu, 13 Aug 2015 13:54:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy7-pub.mail.unifiedlayer.com (gproxy7-pub.mail.unifiedlayer.com [70.40.196.235]) by gabe.freedesktop.org (Postfix) with SMTP id 23F8C6E5C5 for ; Thu, 13 Aug 2015 13:54:46 -0700 (PDT) Received: (qmail 2761 invoked by uid 0); 13 Aug 2015 20:54:44 -0000 Received: from unknown (HELO cmgw3) (10.0.90.84) by gproxy7.mail.unifiedlayer.com with SMTP; 13 Aug 2015 20:54:44 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by cmgw3 with id 4Sug1r01A2UhLwi01SujWa; Thu, 13 Aug 2015 20:54:43 -0600 X-Authority-Analysis: v=2.1 cv=Qc314Krv c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=uRRa74qj2VoA:10 a=oHhwHKnb4EaNSozIirQA:9 a=JBQDAeGROXC7Wbg9:21 a=385BtCnDoRbOsB8v:21 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=hzM0858FUZBcy6tU1ZeFkOTz8wFk5yvnIqsDa3JZ+28=; b=XqkUwjXWTe+nh+E9bZuVN6BtLhf3LLx/71HJ4BwrzveeJf88ET7OXyGyhzDJkvfRUslN0injsIIB/0+tc8qMORWIcolZ/8jn40KY05BoQIyI8WI+d4lS8LhCD85vNHr1; Received: from [67.161.37.189] (port=44094 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:AES128-SHA256:128) (Exim 4.84) (envelope-from ) id 1ZPzAC-0004up-Fh for intel-gfx@lists.freedesktop.org; Thu, 13 Aug 2015 14:31:48 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Aug 2015 13:31:34 -0700 Message-Id: <1439497901-14310-11-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439497901-14310-1-git-send-email-jbarnes@virtuousgeek.org> References: <1439497901-14310-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 11/18] tests/gem_tiled_pread/pwrite: mark normal tests as basic X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP These simple tests should always pass. Signed-off-by: Jesse Barnes --- tests/gem_tiled_pread.c | 167 +++++++++++++++++++++-------------------- tests/gem_tiled_pread_pwrite.c | 48 ++++++------ 2 files changed, 112 insertions(+), 103 deletions(-) diff --git a/tests/gem_tiled_pread.c b/tests/gem_tiled_pread.c index fdc5173..92bb649 100644 --- a/tests/gem_tiled_pread.c +++ b/tests/gem_tiled_pread.c @@ -112,7 +112,7 @@ calculate_expected(int offset) return (base_y + tile_y) * WIDTH + base_x + tile_x; } -igt_simple_main +igt_main { int fd; int i, iter = 100; @@ -120,96 +120,101 @@ igt_simple_main uint32_t handle; uint32_t devid; - fd = drm_open_any(); + igt_fixture { + fd = drm_open_any(); - handle = create_bo(fd); - gem_get_tiling(fd, handle, &tiling, &swizzle); + handle = create_bo(fd); + gem_get_tiling(fd, handle, &tiling, &swizzle); - devid = intel_get_drm_devid(fd); - - if (IS_GEN2(devid)) { - tile_height = 16; - tile_width = 128; - tile_size = 2048; - } else { - tile_height = 8; - tile_width = 512; - tile_size = PAGE_SIZE; + devid = intel_get_drm_devid(fd); } - /* Read a bunch of random subsets of the data and check that they come - * out right. - */ - for (i = 0; i < iter; i++) { - int size = WIDTH * HEIGHT * 4; - int offset = (random() % size) & ~3; - int len = (random() % size) & ~3; - int j; + igt_subtest("basic") { - if (len == 0) - len = 4; + if (IS_GEN2(devid)) { + tile_height = 16; + tile_width = 128; + tile_size = 2048; + } else { + tile_height = 8; + tile_width = 512; + tile_size = PAGE_SIZE; + } - if (offset + len > size) - len = size - offset; + /* Read a bunch of random subsets of the data and check that they come + * out right. + */ + for (i = 0; i < iter; i++) { + int size = WIDTH * HEIGHT * 4; + int offset = (random() % size) & ~3; + int len = (random() % size) & ~3; + int j; - if (i == 0) { - offset = 0; - len = size; - } + if (len == 0) + len = 4; - gem_read(fd, handle, offset, linear, len); + if (offset + len > size) + len = size - offset; - /* Translate from offsets in the read buffer to the swizzled - * address that it corresponds to. This is the opposite of - * what Mesa does (calculate offset to be read given the linear - * offset it's looking for). - */ - for (j = offset; j < offset + len; j += 4) { - uint32_t expected_val, found_val; - int swizzled_offset; - const char *swizzle_str; - - switch (swizzle) { - case I915_BIT_6_SWIZZLE_NONE: - swizzled_offset = j; - swizzle_str = "none"; - break; - case I915_BIT_6_SWIZZLE_9: - swizzled_offset = j ^ - swizzle_bit(9, j); - swizzle_str = "bit9"; - break; - case I915_BIT_6_SWIZZLE_9_10: - swizzled_offset = j ^ - swizzle_bit(9, j) ^ - swizzle_bit(10, j); - swizzle_str = "bit9^10"; - break; - case I915_BIT_6_SWIZZLE_9_11: - swizzled_offset = j ^ - swizzle_bit(9, j) ^ - swizzle_bit(11, j); - swizzle_str = "bit9^11"; - break; - case I915_BIT_6_SWIZZLE_9_10_11: - swizzled_offset = j ^ - swizzle_bit(9, j) ^ - swizzle_bit(10, j) ^ - swizzle_bit(11, j); - swizzle_str = "bit9^10^11"; - break; - default: - igt_assert_f(0, "Bad swizzle bits; %d\n", - swizzle); + if (i == 0) { + offset = 0; + len = size; + } + + gem_read(fd, handle, offset, linear, len); + + /* Translate from offsets in the read buffer to the swizzled + * address that it corresponds to. This is the opposite of + * what Mesa does (calculate offset to be read given the linear + * offset it's looking for). + */ + for (j = offset; j < offset + len; j += 4) { + uint32_t expected_val, found_val; + int swizzled_offset; + const char *swizzle_str; + + switch (swizzle) { + case I915_BIT_6_SWIZZLE_NONE: + swizzled_offset = j; + swizzle_str = "none"; + break; + case I915_BIT_6_SWIZZLE_9: + swizzled_offset = j ^ + swizzle_bit(9, j); + swizzle_str = "bit9"; + break; + case I915_BIT_6_SWIZZLE_9_10: + swizzled_offset = j ^ + swizzle_bit(9, j) ^ + swizzle_bit(10, j); + swizzle_str = "bit9^10"; + break; + case I915_BIT_6_SWIZZLE_9_11: + swizzled_offset = j ^ + swizzle_bit(9, j) ^ + swizzle_bit(11, j); + swizzle_str = "bit9^11"; + break; + case I915_BIT_6_SWIZZLE_9_10_11: + swizzled_offset = j ^ + swizzle_bit(9, j) ^ + swizzle_bit(10, j) ^ + swizzle_bit(11, j); + swizzle_str = "bit9^10^11"; + break; + default: + igt_assert_f(0, "Bad swizzle bits; %d\n", + swizzle); + } + expected_val = calculate_expected(swizzled_offset); + found_val = linear[(j - offset) / 4]; + igt_assert_f(expected_val == found_val, + "Bad read [%d]: %d instead of %d at 0x%08x " + "for read from 0x%08x to 0x%08x, swizzle=%s\n", + i, found_val, expected_val, j, + offset, offset + len, + swizzle_str); } - expected_val = calculate_expected(swizzled_offset); - found_val = linear[(j - offset) / 4]; - igt_assert_f(expected_val == found_val, - "Bad read [%d]: %d instead of %d at 0x%08x " - "for read from 0x%08x to 0x%08x, swizzle=%s\n", - i, found_val, expected_val, j, - offset, offset + len, - swizzle_str); } } diff --git a/tests/gem_tiled_pread_pwrite.c b/tests/gem_tiled_pread_pwrite.c index 3d8fdc9..efb56d5 100644 --- a/tests/gem_tiled_pread_pwrite.c +++ b/tests/gem_tiled_pread_pwrite.c @@ -101,7 +101,7 @@ create_bo(int fd) return handle; } -igt_simple_main +igt_main { int fd; uint32_t *data; @@ -109,34 +109,38 @@ igt_simple_main uint32_t tiling, swizzle; uint32_t handle, handle_target; int count; - - fd = drm_open_any(); - count = SLOW_QUICK(intel_get_total_ram_mb() * 9 / 10, 8) ; - for (i = 0; i < count/2; i++) { - current_tiling_mode = I915_TILING_X; + igt_fixture { + fd = drm_open_any(); + count = SLOW_QUICK(intel_get_total_ram_mb() * 9 / 10, 8); + } + + igt_subtest("basic") { + for (i = 0; i < count/2; i++) { + current_tiling_mode = I915_TILING_X; - handle = create_bo_and_fill(fd); - gem_get_tiling(fd, handle, &tiling, &swizzle); + handle = create_bo_and_fill(fd); + gem_get_tiling(fd, handle, &tiling, &swizzle); - gem_read(fd, handle, 0, linear, sizeof(linear)); + gem_read(fd, handle, 0, linear, sizeof(linear)); - handle_target = create_bo(fd); - gem_write(fd, handle_target, 0, linear, sizeof(linear)); + handle_target = create_bo(fd); + gem_write(fd, handle_target, 0, linear, sizeof(linear)); - /* Check the target bo's contents. */ - data = gem_mmap(fd, handle_target, sizeof(linear), PROT_READ | PROT_WRITE); - for (j = 0; j < WIDTH*HEIGHT; j++) - igt_assert_f(data[j] == j, - "mismatch at %i: %i\n", - j, data[j]); - munmap(data, sizeof(linear)); + /* Check the target bo's contents. */ + data = gem_mmap(fd, handle_target, sizeof(linear), PROT_READ | PROT_WRITE); + for (j = 0; j < WIDTH*HEIGHT; j++) + igt_assert_f(data[j] == j, + "mismatch at %i: %i\n", + j, data[j]); + munmap(data, sizeof(linear)); - /* Leak both bos so that we use all of system mem! */ - gem_madvise(fd, handle_target, I915_MADV_DONTNEED); - gem_madvise(fd, handle, I915_MADV_DONTNEED); + /* Leak both bos so that we use all of system mem! */ + gem_madvise(fd, handle_target, I915_MADV_DONTNEED); + gem_madvise(fd, handle, I915_MADV_DONTNEED); - igt_progress("gem_tiled_pread_pwrite: ", i, count/2); + igt_progress("gem_tiled_pread_pwrite: ", i, count/2); + } } close(fd);