@@ -984,6 +984,7 @@ struct i915_psr {
unsigned busy_frontbuffer_bits;
bool psr2_support;
bool aux_frame_sync;
+ int sw_idle_frame_delay;
};
enum intel_pch {
@@ -364,6 +364,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
+ int frame_time, idle_frames;
if (!HAS_PSR(dev)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -425,6 +427,15 @@ void intel_psr_enable(struct intel_dp *intel_dp)
* to active transition, i.e. here.
*/
vlv_psr_enable_source(intel_dp);
+
+ /*
+ * On VLV/CHV the transition to PSR active happens
+ * immediatelly on SW mode. So we need to simulate
+ * idle_frames to respect panel limitations.
+ */
+ frame_time = DIV_ROUND_UP(1000, drm_mode_vrefresh(mode));
+ idle_frames = dev_priv->vbt.psr.idle_frames + 2;
+ dev_priv->psr.sw_idle_frame_delay = idle_frames * frame_time;
}
/*
@@ -723,7 +734,7 @@ void intel_psr_flush(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
enum pipe pipe;
- int delay_ms = HAS_DDI(dev) ? 0 : 500;
+ int delay_ms = dev_priv->psr.sw_idle_frame_delay;
mutex_lock(&dev_priv->psr.lock);
if (!dev_priv->psr.enabled) {
With commit 30886c5a ("drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.") we fixed a blank screen when first activation was happening immediatelly after PSR being enabled. There we gave more time for idleness by increasing the delay between re-activating sequences. However, commit "drm/i915: Delay first PSR activation." delay the first activation in a better way keeping a good psr residency. So, we can now reduce the delay on re-enable. Unfortunately we cannot reduce to 0 as on core platforms because on SW mode the transiction to active state happens immediatelly and panel needs some idle frames. However instead to reduce it back to 100ms let's propperly calculate the frame time and wait at least 2 frame time so we assure 1 entire vblank period. I also avoided wait_for_vblank to avoid long period block on psr.lock. And also I calculated the time only once per enable so we avoid re-calculating this time every exit. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-)