From patchwork Fri Aug 21 00:55:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 7047461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ECEFEC05AC for ; Fri, 21 Aug 2015 00:55:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E3BA3205C6 for ; Fri, 21 Aug 2015 00:55:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F086D20515 for ; Fri, 21 Aug 2015 00:55:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57EFE6E49D; Thu, 20 Aug 2015 17:55:22 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 50AC46E49D for ; Thu, 20 Aug 2015 17:55:21 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 20 Aug 2015 17:54:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,718,1432623600"; d="scan'208";a="788118086" Received: from rdvivi-hillsboro.jf.intel.com ([10.7.196.156]) by orsmga002.jf.intel.com with ESMTP; 20 Aug 2015 17:54:53 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Thu, 20 Aug 2015 17:55:44 -0700 Message-Id: <1440118544-26282-7-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1440118544-26282-1-git-send-email-rodrigo.vivi@intel.com> References: <1440118544-26282-1-git-send-email-rodrigo.vivi@intel.com> Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Reduce PSR re-activation time for VLV/CHV. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With commit 30886c5a ("drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.") we fixed a blank screen when first activation was happening immediatelly after PSR being enabled. There we gave more time for idleness by increasing the delay between re-activating sequences. However, commit "drm/i915: Delay first PSR activation." delay the first activation in a better way keeping a good psr residency. So, we can now reduce the delay on re-enable. Unfortunately we cannot reduce to 0 as on core platforms because on SW mode the transiction to active state happens immediatelly and panel needs some idle frames. However instead to reduce it back to 100ms let's propperly calculate the frame time and wait at least 2 frame time so we assure 1 entire vblank period. I also avoided wait_for_vblank to avoid long period block on psr.lock. And also I calculated the time only once per enable so we avoid re-calculating this time every exit. Signed-off-by: Rodrigo Vivi Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e0f3f05..0e2cb35 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -984,6 +984,7 @@ struct i915_psr { unsigned busy_frontbuffer_bits; bool psr2_support; bool aux_frame_sync; + int sw_idle_frame_delay; }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a850b7d..7517207 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -364,6 +364,8 @@ void intel_psr_enable(struct intel_dp *intel_dp) struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; + int frame_time, idle_frames; if (!HAS_PSR(dev)) { DRM_DEBUG_KMS("PSR not supported on this platform\n"); @@ -425,6 +427,15 @@ void intel_psr_enable(struct intel_dp *intel_dp) * to active transition, i.e. here. */ vlv_psr_enable_source(intel_dp); + + /* + * On VLV/CHV the transition to PSR active happens + * immediatelly on SW mode. So we need to simulate + * idle_frames to respect panel limitations. + */ + frame_time = DIV_ROUND_UP(1000, drm_mode_vrefresh(mode)); + idle_frames = dev_priv->vbt.psr.idle_frames + 2; + dev_priv->psr.sw_idle_frame_delay = idle_frames * frame_time; } /* @@ -723,7 +734,7 @@ void intel_psr_flush(struct drm_device *dev, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc; enum pipe pipe; - int delay_ms = HAS_DDI(dev) ? 0 : 500; + int delay_ms = dev_priv->psr.sw_idle_frame_delay; mutex_lock(&dev_priv->psr.lock); if (!dev_priv->psr.enabled) {