From patchwork Fri Aug 28 08:40:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gary C Wang X-Patchwork-Id: 7090371 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6781EBEEC1 for ; Fri, 28 Aug 2015 08:35:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89DAF20981 for ; Fri, 28 Aug 2015 08:35:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 627B9205D6 for ; Fri, 28 Aug 2015 08:35:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 318B96E0D1; Fri, 28 Aug 2015 01:35:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 937586E0D1 for ; Fri, 28 Aug 2015 01:35:22 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 28 Aug 2015 01:35:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,424,1437462000"; d="scan'208";a="633864990" Received: from gcwang-linux.itwn.intel.com ([10.241.114.84]) by orsmga003.jf.intel.com with ESMTP; 28 Aug 2015 01:35:21 -0700 From: Gary Wang To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Aug 2015 16:40:34 +0800 Message-Id: <1440751234-12801-1-git-send-email-gary.c.wang@intel.com> X-Mailer: git-send-email 1.9.1 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: set CDCLK if DPLL0 enabled during resuming from S3 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then driver needs to set CDCLK to avoid display corruption if DPLL0 enabled. References: https://bugs.freedesktop.org/show_bug.cgi?id=91697 Reviewed-by: Rodrigo Vivi Reviewed-by: Damien Lespiau Reviewed-by: Cooper Chiou Reviewed-by: Wei Shun Chang Tested-by: Gary Wang Cc: Daniel Vetter Cc: Gavin Hindman Cc: Chris Wilson Cc: Xiong Y Zhang Signed-off-by: Gary Wang Reviewed-by: Damien Lespiau Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/i915/intel_display.c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c old mode 100644 new mode 100755 index f604ce1..617d1d8 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5707,16 +5707,13 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) /* enable PG1 and Misc I/O */ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); - /* DPLL0 already enabed !? */ - if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { - DRM_DEBUG_DRIVER("DPLL0 already running\n"); - return; + /* DPLL0 not enabed !? */ + if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { + /* enable DPLL0 */ + required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); + skl_dpll0_enable(dev_priv, required_vco); } - /* enable DPLL0 */ - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); - skl_dpll0_enable(dev_priv, required_vco); - /* set CDCLK to the frequency the BIOS chose */ skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);