diff mbox

[v2,5/7] drm/i915: Program GuC MAX IDLE Count

Message ID 1442033276-2191-6-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com Sept. 12, 2015, 4:47 a.m. UTC
Cc: Alex Dai <yu.dai@intel.com>
Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c     | 4 ++++
 2 files changed, 5 insertions(+)

Comments

yu.dai@intel.com Sept. 21, 2015, 6:50 p.m. UTC | #1
Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Cc: Alex Dai <yu.dai@intel.com>
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c     | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 8c8e574..9d79a6b 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -53,6 +53,7 @@
>   #define   START_DMA			  (1<<0)
>   #define DMA_GUC_WOPCM_OFFSET		0xc340
>   #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
> +#define GUC_MAX_IDLE_COUNT		0xC3E4
>   
>   #define GUC_WOPCM_SIZE			0xc050
>   #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4d6bb6b..6843a48 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4841,6 +4841,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   	for_each_ring(ring, dev_priv, unused)
>   		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	if (HAS_GUC_UCODE(dev))
> +		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> +
>   	I915_WRITE(GEN6_RC_SLEEP, 0);
>   	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 8c8e574..9d79a6b 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -53,6 +53,7 @@ 
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		0xc340
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
+#define GUC_MAX_IDLE_COUNT		0xC3E4
 
 #define GUC_WOPCM_SIZE			0xc050
 #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d6bb6b..6843a48 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4841,6 +4841,10 @@  static void gen9_enable_rc6(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 	for_each_ring(ring, dev_priv, unused)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	if (HAS_GUC_UCODE(dev))
+		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
+
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */