From patchwork Tue Sep 15 23:31:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yu.dai@intel.com X-Patchwork-Id: 7189631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 97418BEEC1 for ; Tue, 15 Sep 2015 23:32:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A56EE2056C for ; Tue, 15 Sep 2015 23:32:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5DBBF204D1 for ; Tue, 15 Sep 2015 23:32:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C2C7B6E271; Tue, 15 Sep 2015 16:32:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 864196E271 for ; Tue, 15 Sep 2015 16:32:38 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 15 Sep 2015 16:32:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,537,1437462000"; d="scan'208";a="645562195" Received: from alex-hsw.fm.intel.com ([10.19.83.132]) by orsmga003.jf.intel.com with ESMTP; 15 Sep 2015 16:32:38 -0700 From: yu.dai@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 15 Sep 2015 16:31:07 -0700 Message-Id: <1442359867-31500-1-git-send-email-yu.dai@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441929372-26140-6-git-send-email-yu.dai@intel.com> References: <1441929372-26140-6-git-send-email-yu.dai@intel.com> Subject: [Intel-gfx] [PATCH 05/15] drm/i915/guc: Media domain bit needed when notify GuC rc6 state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Dai GuC expects two bits for Render and Media domain separately when driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for Render and bit 1 is for Media domain. v1: Add parameters definition to avoid magic value Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_guc_submission.c | 6 ++++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 38b6ef4..2bea858 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -158,9 +158,11 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, u32 data[2]; data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; - data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0; + /* bit 0 and 1 are for Render and Media domain separately */ + data[1] = (intel_enable_rc6(dev_priv->dev)) ? + GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA : 0; - return host2guc_action(guc, data, 2); + return host2guc_action(guc, data, ARRAY_SIZE(data)); } /* diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index f6d0aa4..ecea053 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -260,6 +260,9 @@ struct guc_context_desc { #define GUC_POWER_D2 3 #define GUC_POWER_D3 4 +#define GUC_FORCEWAKE_RENDER (1 << 0) +#define GUC_FORCEWAKE_MEDIA (1 << 1) + /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ enum host2guc_action { HOST2GUC_ACTION_DEFAULT = 0x0,