diff mbox

[03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS

Message ID 1442595836-23981-4-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Sept. 18, 2015, 5:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

Comments

Jani Nikula Sept. 21, 2015, 7:37 a.m. UTC | #1 
On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e2bf9e2..e6d7a69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> -		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
> +		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
>  
>  	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
>  	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
> @@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	s->pm_ier		= I915_READ(GEN6_PMIER);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> -		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
> +		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
>  
>  	/* GT SA CZ domain, 0x100000-0x138124 */
>  	s->tilectl		= I915_READ(TILECTL);
> @@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> -		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
> +		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>  
>  	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
>  	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
> @@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_PMIER,		s->pm_ier);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> -		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
> +		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
>  
>  	/* GT SA CZ domain, 0x100000-0x138124 */
>  	I915_WRITE(TILECTL,			s->tilectl);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 67bf205..44cedbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
>  #define GEN7_GFX_PEND_TLB0	0x4034
>  #define GEN7_GFX_PEND_TLB1	0x4038
>  /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
> -#define GEN7_LRA_LIMITS_BASE	0x403C
> +#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
>  #define GEN7_LRA_LIMITS_REG_NUM	13
>  #define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
>  #define GEN7_GFX_MAX_REQ_COUNT		0x4074
> @@ -6808,7 +6808,7 @@ enum skl_disp_power_wells {
>  						 GEN6_PM_RP_DOWN_THRESHOLD | \
>  						 GEN6_PM_RP_DOWN_TIMEOUT)
>  
> -#define GEN7_GT_SCRATCH_BASE			0x4F100
> +#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
>  #define GEN7_GT_SCRATCH_REG_NUM			8
>  
>  #define VLV_GTLC_SURVIVABILITY_REG              0x130098
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e2bf9e2..e6d7a69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1120,7 +1120,7 @@  static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
 
 	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
+		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
 
 	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
 	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
@@ -1164,7 +1164,7 @@  static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	s->pm_ier		= I915_READ(GEN6_PMIER);
 
 	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
+		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
 
 	/* GT SA CZ domain, 0x100000-0x138124 */
 	s->tilectl		= I915_READ(TILECTL);
@@ -1202,7 +1202,7 @@  static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
 
 	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
+		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 
 	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
 	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
@@ -1246,7 +1246,7 @@  static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_PMIER,		s->pm_ier);
 
 	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
+		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 
 	/* GT SA CZ domain, 0x100000-0x138124 */
 	I915_WRITE(TILECTL,			s->tilectl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..44cedbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1527,7 +1527,7 @@  enum skl_disp_power_wells {
 #define GEN7_GFX_PEND_TLB0	0x4034
 #define GEN7_GFX_PEND_TLB1	0x4038
 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
-#define GEN7_LRA_LIMITS_BASE	0x403C
+#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
 #define GEN7_LRA_LIMITS_REG_NUM	13
 #define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
 #define GEN7_GFX_MAX_REQ_COUNT		0x4074
@@ -6808,7 +6808,7 @@  enum skl_disp_power_wells {
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define GEN7_GT_SCRATCH_BASE			0x4F100
+#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
 #define GEN7_GT_SCRATCH_REG_NUM			8
 
 #define VLV_GTLC_SURVIVABILITY_REG              0x130098