From patchwork Thu Sep 24 22:53:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 7261661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 44A519F39B for ; Thu, 24 Sep 2015 22:54:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 61AD620899 for ; Thu, 24 Sep 2015 22:54:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3DAFC20887 for ; Thu, 24 Sep 2015 22:54:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51A4E6E85D; Thu, 24 Sep 2015 15:54:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BA216E10F for ; Thu, 24 Sep 2015 15:53:52 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 24 Sep 2015 15:53:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,583,1437462000"; d="scan'208";a="812416371" Received: from mdroper-hswdev.fm.intel.com (HELO mdroper-hswdev) ([10.1.134.215]) by fmsmga002.fm.intel.com with ESMTP; 24 Sep 2015 15:53:52 -0700 Received: from mattrope by mdroper-hswdev with local (Exim 4.84) (envelope-from ) id 1ZfFOi-0002aO-3s; Thu, 24 Sep 2015 15:53:52 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Sep 2015 15:53:06 -0700 Message-Id: <1443135200-9870-2-git-send-email-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443135200-9870-1-git-send-email-matthew.d.roper@intel.com> References: <1443135200-9870-1-git-send-email-matthew.d.roper@intel.com> Subject: [Intel-gfx] [PATCH 01/15] drm/i915: Drop redundant watermark programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,LONGWORDS, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In commit commit e4ca061275ec6a48b66c6edebe08644e666994c0 Author: Patrik Jakobsson Date: Wed Jul 8 15:31:52 2015 +0200 drm/i915: Don't forget to mark crtc as inactive after disable we added extra watermark updates to all of the .crtc_disable() entrypoints to avoid problems problems with system resume on SKL. Those disable entrypoints are currently called in just two places in the driver: intel_atomic_commit (i.e., during a modeset) and intel_crtc_disable_noatomic (which is called during hardware readout). It seems that this extra watermark recalculation should only be important in the latter case (which happens during a resume operation); the former case should always have appropriate watermark programming happening at other points in the modeset sequence. Let's move the watermark update out of the .crtc_disable() entrypoints and place it directly in intel_crtc_disable_noatomic() so that it only happens on S3 resume and not during a regular modeset (since the existing watermark handling should properly update watermarks during normal atomic commits). Cc: Patrik Jakobsson Signed-off-by: Matt Roper Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1847257..dea1f23 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5067,9 +5067,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) ironlake_fdi_pll_disable(intel_crtc); } - - intel_crtc->active = false; - intel_update_watermarks(crtc); } static void haswell_crtc_disable(struct drm_crtc *crtc) @@ -5113,9 +5110,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->post_disable) encoder->post_disable(encoder); - - intel_crtc->active = false; - intel_update_watermarks(crtc); } static void i9xx_pfit_enable(struct intel_crtc *crtc) @@ -6214,9 +6208,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (!IS_GEN2(dev)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - - intel_crtc->active = false; - intel_update_watermarks(crtc); } static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) @@ -6236,6 +6227,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) intel_crtc_disable_planes(crtc, crtc->state->plane_mask); dev_priv->display.crtc_disable(crtc); + intel_crtc->active = false; + intel_update_watermarks(crtc); intel_disable_shared_dpll(intel_crtc); domains = intel_crtc->enabled_power_domains;