diff mbox

[03/12] drm/i915/gen9: Merge two WA as they part of same register

Message ID 1443188026-1222-4-git-send-email-arun.siluvery@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

arun.siluvery@linux.intel.com Sept. 25, 2015, 1:33 p.m. UTC
Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
an entry in WA array.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Comments

Ville Syrjala Sept. 25, 2015, 5:47 p.m. UTC | #1
On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote:
> Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
> an entry in WA array.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 6671800..ad16ef4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>  	}
>  
>  	/* Wa4x4STCOptimizationDisable:skl,bxt */
> -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> -
>  	/* WaDisablePartialResolveInVc:skl,bxt */
> -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> +	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
> +					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
>  	/* WaCcsTlbPrefetchDisable:skl,bxt */
>  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter Sept. 28, 2015, 1:56 p.m. UTC | #2
On Fri, Sep 25, 2015 at 08:47:11PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote:
> > Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
> > an entry in WA array.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
> >  1 file changed, 2 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 6671800..ad16ef4 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >  	}
> >  
> >  	/* Wa4x4STCOptimizationDisable:skl,bxt */
> > -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> > -
> >  	/* WaDisablePartialResolveInVc:skl,bxt */
> > -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> > +	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
> > +					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
> >  
> >  	/* WaCcsTlbPrefetchDisable:skl,bxt */
> >  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6671800..ad16ef4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -946,10 +946,9 @@  static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	}
 
 	/* Wa4x4STCOptimizationDisable:skl,bxt */
-	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
 	/* WaDisablePartialResolveInVc:skl,bxt */
-	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
+					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
 	/* WaCcsTlbPrefetchDisable:skl,bxt */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,