From patchwork Tue Sep 29 21:54:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav K Singh X-Patchwork-Id: 7290611 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 47EAABEEA4 for ; Tue, 29 Sep 2015 21:58:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6C5142068D for ; Tue, 29 Sep 2015 21:58:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 70AE82064F for ; Tue, 29 Sep 2015 21:58:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B21C96E2C2; Tue, 29 Sep 2015 14:58:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id BBD7D6E285 for ; Tue, 29 Sep 2015 14:58:32 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 29 Sep 2015 14:58:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,609,1437462000"; d="scan'208";a="654637414" Received: from gksingh1.iind.intel.com ([10.223.26.37]) by orsmga003.jf.intel.com with ESMTP; 29 Sep 2015 14:58:29 -0700 From: Gaurav K Singh To: intel-gfx Date: Wed, 30 Sep 2015 03:24:10 +0530 Message-Id: <1443563651-11596-14-git-send-email-gaurav.k.singh@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> References: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> Cc: m.deepak@intel.com, suryanarayana.r.sangani@intel.com, rakshmi.bhatia@intel.com Subject: [Intel-gfx] [PATCH 13/14] drm/i915: Reset the display hw if vid mode to cmd mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reset the display hardware if video mode to command mode transition has to be done in MIPI display. otherwise command mode will not work. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi.c | 4 ++++ 3 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3d1700f..7538197 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1954,6 +1954,7 @@ struct drm_i915_private { } gt; bool edp_low_vswing; + bool video_disabled; /* * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0a6676f..5911a333 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6149,6 +6149,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_encoder *encoder; int pipe = intel_crtc->pipe; + bool all_pipe_disabled; + u32 val; /* * On gen2 planes are double buffered but the pipe isn't, so we must @@ -15444,6 +15446,47 @@ void intel_modeset_cleanup(struct drm_device *dev) mutex_lock(&dev->struct_mutex); intel_cleanup_gt_powersave(dev); mutex_unlock(&dev->struct_mutex); + + all_pipe_disabled = true; + for_each_pipe(dev_priv, pipe) { + if ((I915_READ(PIPECONF(pipe)) & + PIPECONF_ENABLE) == PIPECONF_ENABLE) + all_pipe_disabled = false; + } + + if ((all_pipe_disabled == true) && + (dev_priv->video_disabled == true)) { + + /* + * to switch from video mode to command mode, need to reset + * the display. + * FIXME: Even after resetting the display, the first modeset + * works sporadically(2 out of 3 times). Need to fix this. + * FIXME: Need to find a better way of doing this, because + * resetting the display resets all the registers in the + * display controller. Need to save and restore some of these + * required registers. + */ + DRM_DEBUG_KMS("vid mode to cmd mode, reset display\n"); + if (IS_CHERRYVIEW(dev)) { + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); + val = val | DP_SSC_PWR_GATE(0); + vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); + + /* delay to power gate display controller */ + mdelay(5); + + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); + val = val & ~((u32)DP_SSC_MASK(0)); + vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); + + /* delay to power on display controller */ + mdelay(10); + } else + DRM_ERROR("vid mode to cmd mode reset is not done.\n"); + + i915_disable_vga(dev_priv->dev); + } } /* diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 2279859..da8526c 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -462,11 +462,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) u32 temp; u32 port_ctrl; + dev_priv->video_disabled = false; + for_each_dsi_port(port, intel_dsi->ports) { /* de-assert ip_tg_enable signal */ port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); if (is_cmd_mode(intel_dsi)) { + if (I915_READ(MIPI_PORT_CTRL(port)) & DPI_ENABLE) + dev_priv->video_disabled = true; I915_WRITE(port_ctrl, 0); } else { temp = I915_READ(port_ctrl);