From patchwork Tue Sep 29 21:53:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav K Singh X-Patchwork-Id: 7290531 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9EF3FBEEA4 for ; Tue, 29 Sep 2015 21:58:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D360B2064F for ; Tue, 29 Sep 2015 21:58:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8344220695 for ; Tue, 29 Sep 2015 21:58:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E04F6E261; Tue, 29 Sep 2015 14:58:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id F09FA6E15A for ; Tue, 29 Sep 2015 14:58:08 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 29 Sep 2015 14:58:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,609,1437462000"; d="scan'208";a="654637004" Received: from gksingh1.iind.intel.com ([10.223.26.37]) by orsmga003.jf.intel.com with ESMTP; 29 Sep 2015 14:57:57 -0700 From: Gaurav K Singh To: intel-gfx Date: Wed, 30 Sep 2015 03:23:59 +0530 Message-Id: <1443563651-11596-3-git-send-email-gaurav.k.singh@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> References: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> Cc: m.deepak@intel.com, suryanarayana.r.sangani@intel.com, rakshmi.bhatia@intel.com Subject: [Intel-gfx] [PATCH 02/14] drm/i915: Add support for TEAR ON Sequence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For command mode panel, panel's fb enabling and tearing configuration is done as part of TEAR ON sequence. This patch parses and executes TEAR ON sequence for MIPI command mode. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_bios.h | 2 ++ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index 1b7417e..d7fdb10 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -948,6 +948,8 @@ enum mipi_seq { MIPI_SEQ_DISPLAY_ON, MIPI_SEQ_DISPLAY_OFF, MIPI_SEQ_DEASSERT_RESET, + MIPI_SEQ_TEAR_ON, + MIPI_SEQ_TEAR_OFF, MIPI_SEQ_MAX }; diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index feeca59..cacd5b8 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -251,7 +251,9 @@ static const char * const seq_name[] = { "MIPI_SEQ_INIT_OTP", "MIPI_SEQ_DISPLAY_ON", "MIPI_SEQ_DISPLAY_OFF", - "MIPI_SEQ_DEASSERT_RESET" + "MIPI_SEQ_DEASSERT_RESET", + "MIPI_SEQ_TEAR_ON", + "MIPI_SEQ_TEAR_OFF" }; static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data) @@ -320,6 +322,11 @@ static int vbt_panel_prepare(struct drm_panel *panel) sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; generic_exec_sequence(intel_dsi, sequence); + if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) { + sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_TEAR_ON]; + generic_exec_sequence(intel_dsi, sequence); + } + return 0; }