From patchwork Tue Sep 29 21:54:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav K Singh X-Patchwork-Id: 7290541 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7220FBEEA4 for ; Tue, 29 Sep 2015 21:58:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D2FA20695 for ; Tue, 29 Sep 2015 21:58:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 996A22064F for ; Tue, 29 Sep 2015 21:58:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E11216E25B; Tue, 29 Sep 2015 14:58:16 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 23BB26E15A for ; Tue, 29 Sep 2015 14:58:10 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 29 Sep 2015 14:58:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,609,1437462000"; d="scan'208";a="654637128" Received: from gksingh1.iind.intel.com ([10.223.26.37]) by orsmga003.jf.intel.com with ESMTP; 29 Sep 2015 14:58:03 -0700 From: Gaurav K Singh To: intel-gfx Date: Wed, 30 Sep 2015 03:24:01 +0530 Message-Id: <1443563651-11596-5-git-send-email-gaurav.k.singh@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> References: <1443563651-11596-1-git-send-email-gaurav.k.singh@intel.com> Cc: m.deepak@intel.com, suryanarayana.r.sangani@intel.com, rakshmi.bhatia@intel.com Subject: [Intel-gfx] [PATCH 04/14] drm/i915: Calculate bw timer for mipi DBI interface X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch will calculate the bandwidth timer for MIPI DBI interface. If the BW timer value is available from VBT, then value from VBT will be used. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index cacd5b8..7d9094a 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -56,6 +56,11 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) #define CLK_ZERO_CNT_MAX 0xFF #define TRAIL_CNT_MAX 0x1F +#define LP_HDR_FOOT_SIZE 6 +#define BW_LP_NUM_OF_PKT 16 +#define BW_LP_LOAD_SIZE 252 +#define EXTRA_ONE_BYTE 1 + #define NS_KHZ_RATIO 1000000 #define GPI0_NC_0_HV_DDI0_HPD 0x4130 @@ -443,7 +448,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; intel_dsi->rst_timer_val = mipi_config->device_reset_timer; intel_dsi->init_count = mipi_config->master_init_timer; - intel_dsi->bw_timer = mipi_config->dbi_bw_timer; intel_dsi->video_frmt_cfg_bits = mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; @@ -601,6 +605,24 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | clk_zero_cnt << 8 | prepare_cnt; + if (mipi_config->dbi_bw_timer) { + intel_dsi->bw_timer = mipi_config->dbi_bw_timer; + } else { + /* + * bw timer should be more than 16 longs packets containing + * 252 bytes + 2 blanking packets. + * bw timer = 16 long packets * (252 bytes payload for each + * long packet + 6 bytes for long packet header and + * footer) + 12 bytes for 2 blanking packets + 1 + * byte for having more of the above. + */ + intel_dsi->bw_timer = DIV_ROUND_UP(BW_LP_NUM_OF_PKT * + (BW_LP_LOAD_SIZE + LP_HDR_FOOT_SIZE), + intel_dsi->lane_count); + + intel_dsi->bw_timer += (extra_byte_count + EXTRA_ONE_BYTE); + } + /* * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 * + 10UI + Extra Byte Count