diff mbox

[2/2] drm/i915/gen8: Flip the 48b switch

Message ID 1443623779-10640-3-git-send-email-michel.thierry@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Thierry Sept. 30, 2015, 2:36 p.m. UTC 
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.

Note, aliasing PPGTT remains 32b only.

v2: s/full_64b/full_48b/. (Akash)
v3: Add sanitize_enable_ppgtt changes until here. (Akash)
v4: Update param description (Chris)

Cc: Akash Goel <akash.goel@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++++++-
 drivers/gpu/drm/i915/i915_params.c  | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

Comments

Daniel Vetter Oct. 1, 2015, 1:16 p.m. UTC | #1 
On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
> Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
> Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
> 
> Note, aliasing PPGTT remains 32b only.
> 
> v2: s/full_64b/full_48b/. (Akash)
> v3: Add sanitize_enable_ppgtt changes until here. (Akash)
> v4: Update param description (Chris)
> 
> Cc: Akash Goel <akash.goel@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>

Queued for -next, thanks for the patch. Can you please ping someone from
mesa to push the libdrm/mesa patches too?

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++++++-
>  drivers/gpu/drm/i915/i915_params.c  | 2 +-
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 47344d0..2d964a7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -104,9 +104,11 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>  {
>  	bool has_aliasing_ppgtt;
>  	bool has_full_ppgtt;
> +	bool has_full_48bit_ppgtt;
>  
>  	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
>  	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
> +	has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
>  
>  	if (intel_vgpu_active(dev))
>  		has_full_ppgtt = false; /* emulation is too hard */
> @@ -125,6 +127,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>  	if (enable_ppgtt == 2 && has_full_ppgtt)
>  		return 2;
>  
> +	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> +		return 3;
> +
>  #ifdef CONFIG_INTEL_IOMMU
>  	/* Disable ppgtt on SNB if VT-d is on. */
>  	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
> @@ -141,7 +146,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>  	}
>  
>  	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
> -		return 2;
> +		return has_full_48bit_ppgtt ? 3 : 2;
>  	else
>  		return has_aliasing_ppgtt ? 1 : 0;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index ca9b8f6..368df67 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -111,7 +111,7 @@ MODULE_PARM_DESC(enable_hangcheck,
>  module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
>  MODULE_PARM_DESC(enable_ppgtt,
>  	"Override PPGTT usage. "
> -	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
> +	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
>  
>  module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
>  MODULE_PARM_DESC(enable_execlists,
> -- 
> 2.6.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Michel Thierry Oct. 1, 2015, 2:40 p.m. UTC | #2 
On 10/1/2015 2:16 PM, Daniel Vetter wrote:
> On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
>> Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
>> Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
>>
>> Note, aliasing PPGTT remains 32b only.
>>
>> v2: s/full_64b/full_48b/. (Akash)
>> v3: Add sanitize_enable_ppgtt changes until here. (Akash)
>> v4: Update param description (Chris)
>>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>
> Queued for -next, thanks for the patch. Can you please ping someone from
> mesa to push the libdrm/mesa patches too?
>

Sure, I'll start the libdmr-mesa process.

Thanks,
Michel Thierry Oct. 16, 2015, 12:23 p.m. UTC | #3 
On 10/1/2015 2:16 PM, Daniel Vetter wrote:
> On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
>> Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
>> Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
>>
>> Note, aliasing PPGTT remains 32b only.
>>
>> v2: s/full_64b/full_48b/. (Akash)
>> v3: Add sanitize_enable_ppgtt changes until here. (Akash)
>> v4: Update param description (Chris)
>>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>
> Queued for -next, thanks for the patch. Can you please ping someone from
> mesa to push the libdrm/mesa patches too?
>
> Cheers, Daniel
>

Sorry I didn't report this earlier, but I just realized I can't find 
this patch in the tree.

There's still the discussion of where to apply the 32-bit workaround and 
the different behavior seen in mesa (not if it isn't needed)... but the 
code was written to not require that flag in order to start using the 
4-level page translation.

Thanks,

-Michel

>> ---
>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++++++-
>>   drivers/gpu/drm/i915/i915_params.c  | 2 +-
>>   2 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 47344d0..2d964a7 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -104,9 +104,11 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>>   {
>>   	bool has_aliasing_ppgtt;
>>   	bool has_full_ppgtt;
>> +	bool has_full_48bit_ppgtt;
>>
>>   	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
>>   	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
>> +	has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
>>
>>   	if (intel_vgpu_active(dev))
>>   		has_full_ppgtt = false; /* emulation is too hard */
>> @@ -125,6 +127,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>>   	if (enable_ppgtt == 2 && has_full_ppgtt)
>>   		return 2;
>>
>> +	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
>> +		return 3;
>> +
>>   #ifdef CONFIG_INTEL_IOMMU
>>   	/* Disable ppgtt on SNB if VT-d is on. */
>>   	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
>> @@ -141,7 +146,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>>   	}
>>
>>   	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
>> -		return 2;
>> +		return has_full_48bit_ppgtt ? 3 : 2;
>>   	else
>>   		return has_aliasing_ppgtt ? 1 : 0;
>>   }
>> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>> index ca9b8f6..368df67 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -111,7 +111,7 @@ MODULE_PARM_DESC(enable_hangcheck,
>>   module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
>>   MODULE_PARM_DESC(enable_ppgtt,
>>   	"Override PPGTT usage. "
>> -	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
>> +	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
>>
>>   module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
>>   MODULE_PARM_DESC(enable_execlists,
>> --
>> 2.6.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
Daniel Vetter Oct. 19, 2015, 9:44 a.m. UTC | #4 
On Fri, Oct 16, 2015 at 01:23:41PM +0100, Michel Thierry wrote:
> On 10/1/2015 2:16 PM, Daniel Vetter wrote:
> >On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
> >>Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
> >>Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
> >>
> >>Note, aliasing PPGTT remains 32b only.
> >>
> >>v2: s/full_64b/full_48b/. (Akash)
> >>v3: Add sanitize_enable_ppgtt changes until here. (Akash)
> >>v4: Update param description (Chris)
> >>
> >>Cc: Akash Goel <akash.goel@intel.com>
> >>Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> >
> >Queued for -next, thanks for the patch. Can you please ping someone from
> >mesa to push the libdrm/mesa patches too?
> >
> >Cheers, Daniel
> >
> 
> Sorry I didn't report this earlier, but I just realized I can't find this
> patch in the tree.

Indeed I seem to have never pushed it. Sorry.

> There's still the discussion of where to apply the 32-bit workaround and the
> different behavior seen in mesa (not if it isn't needed)... but the code was
> written to not require that flag in order to start using the 4-level page
> translation.

Queued for -next, thanks for the patch.
-Daniel
Chris Wilson Oct. 19, 2015, 10:01 a.m. UTC | #5 
On Mon, Oct 19, 2015 at 11:44:12AM +0200, Daniel Vetter wrote:
> On Fri, Oct 16, 2015 at 01:23:41PM +0100, Michel Thierry wrote:
> > On 10/1/2015 2:16 PM, Daniel Vetter wrote:
> > >On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
> > >>Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
> > >>Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
> > >>
> > >>Note, aliasing PPGTT remains 32b only.
> > >>
> > >>v2: s/full_64b/full_48b/. (Akash)
> > >>v3: Add sanitize_enable_ppgtt changes until here. (Akash)
> > >>v4: Update param description (Chris)
> > >>
> > >>Cc: Akash Goel <akash.goel@intel.com>
> > >>Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > >>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > >
> > >Queued for -next, thanks for the patch. Can you please ping someone from
> > >mesa to push the libdrm/mesa patches too?
> > >
> > >Cheers, Daniel
> > >
> > 
> > Sorry I didn't report this earlier, but I just realized I can't find this
> > patch in the tree.
> 
> Indeed I seem to have never pushed it. Sorry.
> 
> > There's still the discussion of where to apply the 32-bit workaround and the
> > different behavior seen in mesa (not if it isn't needed)... but the code was
> > written to not require that flag in order to start using the 4-level page
> > translation.
> 
> Queued for -next, thanks for the patch.

We never got an answer whether there was any impact on existing
userspace which is constained to 4GiB (where the last level of
pagetables are superfluous).
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47344d0..2d964a7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -104,9 +104,11 @@  static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 {
 	bool has_aliasing_ppgtt;
 	bool has_full_ppgtt;
+	bool has_full_48bit_ppgtt;
 
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
+	has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
 
 	if (intel_vgpu_active(dev))
 		has_full_ppgtt = false; /* emulation is too hard */
@@ -125,6 +127,9 @@  static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 
+	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+		return 3;
+
 #ifdef CONFIG_INTEL_IOMMU
 	/* Disable ppgtt on SNB if VT-d is on. */
 	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
@@ -141,7 +146,7 @@  static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 	}
 
 	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
-		return 2;
+		return has_full_48bit_ppgtt ? 3 : 2;
 	else
 		return has_aliasing_ppgtt ? 1 : 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index ca9b8f6..368df67 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -111,7 +111,7 @@  MODULE_PARM_DESC(enable_hangcheck,
 module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
 MODULE_PARM_DESC(enable_ppgtt,
 	"Override PPGTT usage. "
-	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
+	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
 
 module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
 MODULE_PARM_DESC(enable_execlists,